Lines Matching defs:BIT_4
186 #define BIT_4 (1 << 4)
304 #define PCI_EXT_PATCH_0 BIT_4
335 #define PCI_ASPM_FORCE_CLKREQ_ENA BIT_4 /* Force CLKREQ Enable (A1b only) */
368 #define PCI_GAT_PME_DE_ASSERTED BIT_4 /* PME De-Asserted */
398 #define PEX_DC_EN_REL_ORD BIT_4 /* Enable Relaxed Ordering */
421 #define PEX_DATA_LINK_P BIT_4 /* Data Link Protocol Error */
798 #define CS_STOP_MAST BIT_4 /* Command Bit to stop the master */
811 #define PC_VCC_DIS BIT_4 /* Switch VCC Disable */
841 #define Y2_IS_IRQ_PHY1 BIT_4 /* Interrupt from PHY 1 */
874 #define Y2_IS_PAR_WR1 BIT_4 /* Write RAM parity error interrupt */
935 #define Y2_PCI_CLK_LNK2_DIS BIT_4 /* Disable PCI clock Link 2 */
989 #define TST_FRC_DPERR_TW BIT_4 /* force DATAPERR on TRG WR */
1011 #define I2C_BURST_LEN BIT_4 /* Burst Len, 1/4 bytes */
1074 #define TXA_DIS_ALLOC BIT_4 /* Disable alloc of free bandwidth */
1082 #define TXA_INT_T_OFF BIT_4 /* Tx Arb Interval Timer Test Off */
1110 #define BMU_FIFO_RST BIT_4 /* Reset FIFO */
1168 #define RB_WP_INC BIT_4 /* Write Pointer Increment */
1175 #define RB_DIS_STFWD BIT_4 /* Disable Store & Forward */
1232 #define WOL_CTL_DIS_LINK_CHG_UNIT BIT_4
1383 #define PHY_M_PC_DIS_125CLK BIT_4 /* Disable 125 CLK */
1431 #define PHY_M_PS_ENDET_STAT BIT_4 /* Energy Detect Status (1=act) */
1456 #define PHY_M_IS_END_CHANGE BIT_4 /* Energy Detect Changed */
1550 #define PHY_M_EC2_FO_M_CLK BIT_4 /* Fiber Mode Clock Enable */
1564 #define PHY_M_DTE_POW_STAT BIT_4 /* DTE Power Status (88E1111 only) */
1819 #define GM_GPSR_GIG_SPEED BIT_4 /* Gigabit Speed (1 = 1000 Mbps) */
1834 #define GM_GPCR_FC_RX_DIS BIT_4 /* Disable Rx Flow-Control Mode */
1896 #define GM_SMI_CT_RD_VAL BIT_4 /* Read Valid (Read completed) */
1904 #define GM_PAR_MIB_TST BIT_4 /* MIB Load Counter (Test Mode) */
1917 #define GMR_FS_LONG_ERR BIT_4 /* Too Long Packet */
1975 #define GMF_CLI_RX_FC BIT_4 /* Clear IRQ Rx Frame Complete */
1994 #define GMF_CLI_TX_PE BIT_4 /* Clear IRQ Tx Parity Error */
2010 #define PC_POLL_RQ BIT_4 /* Poll Request Start */
2018 #define Y2_ASF_OS_PRES BIT_4 /* ASF operation system present */
2037 #define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE1 BIT_4
2039 #define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_MSK (BIT_4 | BIT_3) /* CPU Clock Divide */
2055 #define SC_STAT_CLR_IRQ BIT_4 /* Status Burst IRQ clear */
2073 #define GMC_F_LOOPB_OFF BIT_4 /* FIFO Loopback Off */
2107 #define GM_IS_TX_CO_OV BIT_4 /* Transmit Counter Overflow IRQ */