dev/msk/if_msk.c

657 			    Y2_PREF_Q_ADDR(sc_if->msk_rxq,
687 		    Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG),
752 	    Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG),
820 	    Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG),
1619 		sc_if->msk_rxq = Q_R1;
1623 		sc_if->msk_rxq = Q_R2;
3482 		CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR);
3592 	CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq,
4001 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET);
4002 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT);
4003 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON);
4004 	CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM);
4008                 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS);
4022 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), reg);
4024 		msk_set_prefetch(sc, sc_if->msk_rxq,
4029 		msk_set_prefetch(sc, sc_if->msk_rxq,
4091 	CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR);
4092 	CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_START),
4094 	CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_END),
4096 	CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_WP),
4098 	CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RP),
4107 	CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_UTPP), utpp);
4108 	CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_LTPP), ltpp);
4111 	CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD);
4112 	CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL));
4248 	CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_DIS_OP_MD);
4250 		if (CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RSL)) ==
4251 		    CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RL)))
4257 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR),
4260 	CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_CTRL_REG),
4263 	CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_SET);