isci/scil/scu_registers.h

61  * mapped registers.
727 //* Port Task Scheduler registers shift and mask values
911 // These registers are based off of BAR0
961  * @brief These are the SMU registers
1037 // MSI-X registers not included
1058  *        See SCU SDMA specification on how these registers are used.
1128  * @brief These are the SCU Transport Layer registers see SSPTL spec for how
1262  *        See the SCU SSLL Specification on how these registers are used.
1431  *        See the SCU SGPIO Specification on how these registers are used.
1466    U32 registers[256];
1497  *        See the SCU SCHED Specification on how these registers are used.
1510  * @brief These are the PORT Task Scheduler registers
1511  *        See the SCU SCHED Specification on how these registers are used.
1641  *        See SCU AFE Specification for use of these registers.
1746  *        See SCU AFE Specification for use of these registers.
1836    /* Uaoa AFE registers */
1984  * @brief FBRAM registers. MMR base address for FBRAM is
2012 * @brief Placeholder for the scratch RAM registers.
2021  * @brief Placeholder since I am not yet sure what these registers are here
2031  * @brief Placeholder since I am not yet sure what these registers are here
2041  * @brief Placeholder since I am not yet sure what these registers are here
2053  * @brief The SCU Hardware pairs up the TL registers with the LL registers
2054  *        so we must place them adjcent to make the array of registers in
2068  *        registers are unique to each protocol engine group.  There can be
2087  * @brief SCU regsiters including both PEG registers if we turn on that
2089  *        All of these registers are in the memory mapped space returned
2091  *        See SCU SMU Specification for how these registers are mapped.