dev/fb/vga.c

804 	outb(adp->va_crtc_addr, 7);
1072     outb(biosadapter[V_ADP_PRIMARY].va_crtc_addr, 12);
1073     outb(biosadapter[V_ADP_PRIMARY].va_crtc_addr + 1, 0);
1074     outb(biosadapter[V_ADP_PRIMARY].va_crtc_addr, 13);
1075     outb(biosadapter[V_ADP_PRIMARY].va_crtc_addr + 1, 0);
1267     outb(adp->va_crtc_addr, 0x13);
1268     outb(adp->va_crtc_addr + 1, count);
1291 	    outb(TSIDX, 1);
1309     outb(adp->va_crtc_addr, 0xc);		/* high */
1310     outb(adp->va_crtc_addr + 1, off >> 8);
1311     outb(adp->va_crtc_addr, 0xd);		/* low */
1312     outb(adp->va_crtc_addr + 1, off & 0xff);
1317 	outb(ATC, 0x13 | 0x20);
1318 	outb(ATC, poff);
1320 	outb(ATC, 0x20);
1324     outb(adp->va_crtc_addr, 8);
1325     outb(adp->va_crtc_addr + 1, roff);
1679 	outb(TSIDX, 0x02); buf[0] = inb(TSREG);
1680 	outb(TSIDX, 0x04); buf[1] = inb(TSREG);
1681 	outb(GDCIDX, 0x04); buf[2] = inb(GDCREG);
1682 	outb(GDCIDX, 0x05); buf[3] = inb(GDCREG);
1683 	outb(GDCIDX, 0x06); buf[4] = inb(GDCREG);
1685 	outb(ATC, 0x10); buf[5] = inb(ATC + 1);
1702     outb(ATC, 0x10); outb(ATC, buf[5] & ~0x01);
1704     outb(ATC, 0x20);				/* enable palette */
1708     outb(TSIDX, 0x00); outb(TSREG, 0x01);
1710     outb(TSIDX, 0x02); outb(TSREG, 0x04);
1711     outb(TSIDX, 0x04); outb(TSREG, 0x07);
1713     outb(TSIDX, 0x00); outb(TSREG, 0x03);
1715     outb(GDCIDX, 0x04); outb(GDCREG, 0x02);
1716     outb(GDCIDX, 0x05); outb(GDCREG, 0x00);
1717     outb(GDCIDX, 0x06); outb(GDCREG, 0x04);
1744     outb(ATC, 0x10); outb(ATC, buf[5]);
1746     outb(ATC, 0x20);				/* enable palette */
1750     outb(TSIDX, 0x00); outb(TSREG, 0x01);
1752     outb(TSIDX, 0x02); outb(TSREG, buf[0]);
1753     outb(TSIDX, 0x04); outb(TSREG, buf[1]);
1755     outb(TSIDX, 0x00); outb(TSREG, 0x03);
1757     outb(GDCIDX, 0x04); outb(GDCREG, buf[2]);
1758     outb(GDCIDX, 0x05); outb(GDCREG, buf[3]);
1760 	outb(GDCIDX, 0x06); outb(GDCREG,(buf[4] & 0x03) | 0x08);
1762 	outb(GDCIDX, 0x06); outb(GDCREG,(buf[4] & 0x03) | 0x0c);
1829 	outb(TSIDX, 0x00); outb(TSREG, 0x01);
1830 	outb(TSIDX, 0x01); val = inb(TSREG);	/* disable screen */
1831 	outb(TSIDX, 0x01); outb(TSREG, val | 0x20);
1832 	outb(TSIDX, 0x00); outb(TSREG, 0x03);
1851 	outb(TSIDX, 0x00); outb(TSREG, 0x01);
1852 	outb(TSIDX, 0x01); outb(TSREG, val & 0xdf);	/* enable screen */
1853 	outb(TSIDX, 0x00); outb(TSREG, 0x03);
1909 	outb(TSIDX, 0x00); outb(TSREG, 0x01);
1910 	outb(TSIDX, 0x01); val = inb(TSREG);	/* disable screen */
1911 	outb(TSIDX, 0x01); outb(TSREG, val | 0x20);
1912 	outb(TSIDX, 0x00); outb(TSREG, 0x03);
1931 	outb(TSIDX, 0x00); outb(TSREG, 0x01);
1932 	outb(TSIDX, 0x01); outb(TSREG, val & 0xdf);	/* enable screen */
1933 	outb(TSIDX, 0x00); outb(TSREG, 0x03);
1964     outb(TSIDX, 0x03); outb(TSREG, cg[page]);
1991     outb(PALRADR, 0x00);
2008     outb(PALRADR, base);
2033     outb(PIXMASK, 0xff);		/* no pixelmask */
2034     outb(PALWADR, 0x00);
2037 	outb(PALDATA, palette[i] >> bits);
2039     outb(ATC, 0x20);			/* enable palette */
2052     outb(PIXMASK, 0xff);		/* no pixelmask */
2053     outb(PALWADR, base);
2056 	outb(PALDATA, r[i] >> bits);
2057 	outb(PALDATA, g[i] >> bits);
2058 	outb(PALDATA, b[i] >> bits);
2061     outb(ATC, 0x20);			/* enable palette */
2080 	outb(ATC, 0x31); outb(ATC, color & 0xff);
2083 	outb(adp->va_crtc_addr + 5, color & 0x0f); /* color select register */
2127     outb(TSIDX, 0x00); outb(TSREG, 0x01);	/* stop sequencer */
2129 	outb(TSIDX, i + 1);
2133     outb(TSIDX, 0x00); outb(TSREG, 0x03);	/* start sequencer */
2136 	outb(crtc_addr, i);
2141 	outb(ATC, i);
2145 	outb(GDCIDX, i);
2149     outb(ATC, 0x20);				/* enable palette */
2208     outb(TSIDX, 0x00); outb(TSREG, 0x01);	/* stop sequencer */
2210 	outb(TSIDX, i + 1);
2211 	outb(TSREG, buf[i + 5]);
2213     outb(MISC, buf[9]);				/* set dot-clock */
2214     outb(TSIDX, 0x00); outb(TSREG, 0x03);	/* start sequencer */
2215     outb(crtc_addr, 0x11);
2216     outb(crtc_addr + 1, inb(crtc_addr + 1) & 0x7F);
2218 	outb(crtc_addr, i);
2219 	outb(crtc_addr + 1, buf[i + 10]);
2223 	outb(ATC, i);
2224 	outb(ATC, buf[i + 35]);
2227 	outb(GDCIDX, i);
2228 	outb(GDCREG, buf[i + 55]);
2231     outb(ATC, 0x20);				/* enable palette */
2284     outb(adp->va_crtc_addr, 14);
2286     outb(adp->va_crtc_addr, 15);
2321     outb(adp->va_crtc_addr, 14);
2322     outb(adp->va_crtc_addr + 1, off >> 8);
2323     outb(adp->va_crtc_addr, 15);
2324     outb(adp->va_crtc_addr + 1, off & 0x00ff);
2355 	    outb(adp->va_crtc_addr, 10);
2356 	    outb(adp->va_crtc_addr + 1, 32);
2357 	    outb(adp->va_crtc_addr, 11);
2358 	    outb(adp->va_crtc_addr + 1, 0);
2360 	    outb(adp->va_crtc_addr, 10);
2361 	    outb(adp->va_crtc_addr + 1, celsize - base - height);
2362 	    outb(adp->va_crtc_addr, 11);
2363 	    outb(adp->va_crtc_addr + 1, celsize - base - 1);
2369 	    outb(adp->va_crtc_addr, 10);
2370 	    outb(adp->va_crtc_addr + 1, celsize);
2371 	    outb(adp->va_crtc_addr, 11);
2372 	    outb(adp->va_crtc_addr + 1, 0);
2374 	    outb(adp->va_crtc_addr, 10);
2375 	    outb(adp->va_crtc_addr + 1, celsize - base - height);
2376 	    outb(adp->va_crtc_addr, 11);
2377 	    outb(adp->va_crtc_addr + 1, celsize - base);
2404 	    outb(TSIDX, 0x01);
2406 	    outb(TSIDX, 0x01);
2407 	    outb(TSREG, val | 0x20);
2408 	    outb(adp->va_crtc_addr, 0x17);
2410 	    outb(adp->va_crtc_addr + 1, val & ~0x80);
2413 	    outb(TSIDX, 0x01);
2415 	    outb(TSIDX, 0x01);
2416 	    outb(TSREG, val | 0x20);
2419 	    outb(TSIDX, 0x01);
2421 	    outb(TSIDX, 0x01);
2422 	    outb(TSREG, val & 0xDF);
2423 	    outb(adp->va_crtc_addr, 0x17);
2425 	    outb(adp->va_crtc_addr + 1, val | 0x80);
2440 	    outb(adp->va_crtc_addr + 4, 0x25);
2443 	    outb(adp->va_crtc_addr + 4, 0x2d);
2454 	    outb(adp->va_crtc_addr + 4, 0x21);
2457 	    outb(adp->va_crtc_addr + 4, 0x29);