dev/e1000/e1000_mac.c

176 	s32 ret_val = E1000_SUCCESS;
215 	return ret_val;
230 	s32 ret_val;
237 	ret_val = e1000_read_pcie_cap_reg(hw, PCIE_LINK_STATUS,
239 	if (ret_val) {
397 	s32 ret_val;
403 	ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data);
404 	if (ret_val)
405 		return ret_val;
417 	ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
419 	if (ret_val) {
421 		return ret_val;
438 		ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
439 		if (ret_val) {
441 			return ret_val;
704 	s32 ret_val;
721 	ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
722 	if (ret_val)
723 		return ret_val;
752 	ret_val = e1000_config_fc_after_link_up_generic(hw);
753 	if (ret_val)
756 	return ret_val;
772 	s32 ret_val;
805 		ret_val = e1000_config_fc_after_link_up_generic(hw);
806 		if (ret_val) {
808 			return ret_val;
839 	s32 ret_val;
870 		ret_val = e1000_config_fc_after_link_up_generic(hw);
871 		if (ret_val) {
873 			return ret_val;
941 	s32 ret_val;
954 	ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
956 	if (ret_val) {
958 		return ret_val;
984 	s32 ret_val;
998 		ret_val = e1000_set_default_fc_generic(hw);
999 		if (ret_val)
1000 			return ret_val;
1012 	ret_val = hw->mac.ops.setup_physical_interface(hw);
1013 	if (ret_val)
1014 		return ret_val;
1111 	s32 ret_val;
1135 		ret_val = mac->ops.check_for_link(hw);
1136 		if (ret_val) {
1138 			return ret_val;
1159 	s32 ret_val;
1170 	ret_val = e1000_commit_fc_settings_generic(hw);
1171 	if (ret_val)
1172 		return ret_val;
1192 		ret_val = e1000_poll_fiber_serdes_link_generic(hw);
1197 	return ret_val;
1334 	s32 ret_val = E1000_SUCCESS;
1348 			ret_val = e1000_force_mac_fc_generic(hw);
1351 			ret_val = e1000_force_mac_fc_generic(hw);
1354 	if (ret_val) {
1356 		return ret_val;
1369 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1370 		if (ret_val)
1371 			return ret_val;
1372 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1373 		if (ret_val)
1374 			return ret_val;
1378 			return ret_val;
1387 		ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
1389 		if (ret_val)
1390 			return ret_val;
1391 		ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
1393 		if (ret_val)
1394 			return ret_val;
1484 		ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1485 		if (ret_val) {
1487 			return ret_val;
1496 		ret_val = e1000_force_mac_fc_generic(hw);
1497 		if (ret_val) {
1499 			return ret_val;
1517 			return ret_val;
1620 		ret_val = e1000_force_mac_fc_generic(hw);
1621 		if (ret_val) {
1623 			return ret_val;
1796 	s32 ret_val;
1800 	ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1801 	if (ret_val) {
1803 		return ret_val;
1820 	s32 ret_val;
1829 	ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1830 	if (ret_val)
1831 		return ret_val;