Lines Matching refs:hw
37 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw);
38 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
39 static void e1000_config_collision_dist_generic(struct e1000_hw *hw);
40 static void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index);
44 * @hw: pointer to the HW structure
48 void e1000_init_mac_ops_generic(struct e1000_hw *hw)
50 struct e1000_mac_info *mac = &hw->mac;
86 * @hw: pointer to the HW structure
88 s32 e1000_null_ops_generic(struct e1000_hw *hw)
96 * @hw: pointer to the HW structure
98 void e1000_null_mac_generic(struct e1000_hw *hw)
106 * @hw: pointer to the HW structure
108 s32 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d)
116 * @hw: pointer to the HW structure
118 bool e1000_null_mng_mode(struct e1000_hw *hw) {
125 * @hw: pointer to the HW structure
127 void e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a)
135 * @hw: pointer to the HW structure
137 void e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b)
145 * @hw: pointer to the HW structure
147 void e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a)
155 * @hw: pointer to the HW structure
157 s32 e1000_null_set_obff_timer(struct e1000_hw *hw, u32 a)
165 * @hw: pointer to the HW structure
171 s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw)
173 struct e1000_mac_info *mac = &hw->mac;
174 struct e1000_bus_info *bus = &hw->bus;
175 u32 status = E1000_READ_REG(hw, E1000_STATUS);
213 mac->ops.set_lan_id(hw);
220 * @hw: pointer to the HW structure
226 s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw)
228 struct e1000_mac_info *mac = &hw->mac;
229 struct e1000_bus_info *bus = &hw->bus;
237 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_LINK_STATUS,
259 mac->ops.set_lan_id(hw);
267 * @hw: pointer to the HW structure
272 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
274 struct e1000_bus_info *bus = &hw->bus;
280 reg = E1000_READ_REG(hw, E1000_STATUS);
286 * @hw: pointer to the HW structure
290 void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw)
292 struct e1000_bus_info *bus = &hw->bus;
296 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type);
298 status = E1000_READ_REG(hw, E1000_STATUS);
308 * @hw: pointer to the HW structure
312 void e1000_set_lan_id_single_port(struct e1000_hw *hw)
314 struct e1000_bus_info *bus = &hw->bus;
321 * @hw: pointer to the HW structure
326 void e1000_clear_vfta_generic(struct e1000_hw *hw)
333 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
334 E1000_WRITE_FLUSH(hw);
340 * @hw: pointer to the HW structure
347 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
351 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
352 E1000_WRITE_FLUSH(hw);
357 * @hw: pointer to the HW structure
364 void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count)
374 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
379 hw->mac.ops.rar_set(hw, mac_addr, i);
384 * @hw: pointer to the HW structure
394 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
403 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data);
408 if ((hw->mac.type < e1000_82571) || (hw->mac.type == e1000_82573))
414 if (hw->mac.type >= e1000_82580)
417 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
429 if (hw->bus.func == E1000_FUNC_1)
431 if (hw->bus.func == E1000_FUNC_2)
434 if (hw->bus.func == E1000_FUNC_3)
438 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
458 hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
465 * @hw: pointer to the HW structure
472 static void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
494 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
495 E1000_WRITE_FLUSH(hw);
496 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
497 E1000_WRITE_FLUSH(hw);
502 * @hw: pointer to the HW structure
508 u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr)
516 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
549 switch (hw->mac.mc_filter_type) {
572 * @hw: pointer to the HW structure
579 void e1000_update_mc_addr_list_generic(struct e1000_hw *hw,
588 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
592 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list);
594 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
597 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
602 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
603 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);
604 E1000_WRITE_FLUSH(hw);
609 * @hw: pointer to the HW structure
616 void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw)
626 if (hw->bus.type != e1000_bus_type_pcix)
629 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
630 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
640 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
646 * @hw: pointer to the HW structure
650 void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw)
654 E1000_READ_REG(hw, E1000_CRCERRS);
655 E1000_READ_REG(hw, E1000_SYMERRS);
656 E1000_READ_REG(hw, E1000_MPC);
657 E1000_READ_REG(hw, E1000_SCC);
658 E1000_READ_REG(hw, E1000_ECOL);
659 E1000_READ_REG(hw, E1000_MCC);
660 E1000_READ_REG(hw, E1000_LATECOL);
661 E1000_READ_REG(hw, E1000_COLC);
662 E1000_READ_REG(hw, E1000_DC);
663 E1000_READ_REG(hw, E1000_SEC);
664 E1000_READ_REG(hw, E1000_RLEC);
665 E1000_READ_REG(hw, E1000_XONRXC);
666 E1000_READ_REG(hw, E1000_XONTXC);
667 E1000_READ_REG(hw, E1000_XOFFRXC);
668 E1000_READ_REG(hw, E1000_XOFFTXC);
669 E1000_READ_REG(hw, E1000_FCRUC);
670 E1000_READ_REG(hw, E1000_GPRC);
671 E1000_READ_REG(hw, E1000_BPRC);
672 E1000_READ_REG(hw, E1000_MPRC);
673 E1000_READ_REG(hw, E1000_GPTC);
674 E1000_READ_REG(hw, E1000_GORCL);
675 E1000_READ_REG(hw, E1000_GORCH);
676 E1000_READ_REG(hw, E1000_GOTCL);
677 E1000_READ_REG(hw, E1000_GOTCH);
678 E1000_READ_REG(hw, E1000_RNBC);
679 E1000_READ_REG(hw, E1000_RUC);
680 E1000_READ_REG(hw, E1000_RFC);
681 E1000_READ_REG(hw, E1000_ROC);
682 E1000_READ_REG(hw, E1000_RJC);
683 E1000_READ_REG(hw, E1000_TORL);
684 E1000_READ_REG(hw, E1000_TORH);
685 E1000_READ_REG(hw, E1000_TOTL);
686 E1000_READ_REG(hw, E1000_TOTH);
687 E1000_READ_REG(hw, E1000_TPR);
688 E1000_READ_REG(hw, E1000_TPT);
689 E1000_READ_REG(hw, E1000_MPTC);
690 E1000_READ_REG(hw, E1000_BPTC);
695 * @hw: pointer to the HW structure
701 s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw)
703 struct e1000_mac_info *mac = &hw->mac;
721 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
733 e1000_check_downshift_generic(hw);
745 mac->ops.config_collision_dist(hw);
752 ret_val = e1000_config_fc_after_link_up_generic(hw);
761 * @hw: pointer to the HW structure
766 s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw)
768 struct e1000_mac_info *mac = &hw->mac;
776 ctrl = E1000_READ_REG(hw, E1000_CTRL);
777 status = E1000_READ_REG(hw, E1000_STATUS);
778 rxcw = E1000_READ_REG(hw, E1000_RXCW);
797 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
800 ctrl = E1000_READ_REG(hw, E1000_CTRL);
802 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
805 ret_val = e1000_config_fc_after_link_up_generic(hw);
817 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
818 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
828 * @hw: pointer to the HW structure
833 s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
835 struct e1000_mac_info *mac = &hw->mac;
843 ctrl = E1000_READ_REG(hw, E1000_CTRL);
844 status = E1000_READ_REG(hw, E1000_STATUS);
845 rxcw = E1000_READ_REG(hw, E1000_RXCW);
862 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
865 ctrl = E1000_READ_REG(hw, E1000_CTRL);
867 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
870 ret_val = e1000_config_fc_after_link_up_generic(hw);
882 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
883 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
886 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) {
893 rxcw = E1000_READ_REG(hw, E1000_RXCW);
905 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) {
906 status = E1000_READ_REG(hw, E1000_STATUS);
910 rxcw = E1000_READ_REG(hw, E1000_RXCW);
934 * @hw: pointer to the HW structure
939 s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
951 * control setting, then the variable hw->fc will
954 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
962 hw->fc.requested_mode = e1000_fc_none;
965 hw->fc.requested_mode = e1000_fc_tx_pause;
967 hw->fc.requested_mode = e1000_fc_full;
974 * @hw: pointer to the HW structure
982 s32 e1000_setup_link_generic(struct e1000_hw *hw)
991 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
997 if (hw->fc.requested_mode == e1000_fc_default) {
998 ret_val = e1000_set_default_fc_generic(hw);
1006 hw->fc.current_mode = hw->fc.requested_mode;
1009 hw->fc.current_mode);
1012 ret_val = hw->mac.ops.setup_physical_interface(hw);
1022 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
1023 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1024 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
1026 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
1028 return e1000_set_fc_watermarks_generic(hw);
1033 * @hw: pointer to the HW structure
1038 s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
1040 struct e1000_mac_info *mac = &hw->mac;
1061 switch (hw->fc.current_mode) {
1094 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1102 * @hw: pointer to the HW structure
1107 s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
1109 struct e1000_mac_info *mac = &hw->mac;
1123 status = E1000_READ_REG(hw, E1000_STATUS);
1135 ret_val = mac->ops.check_for_link(hw);
1151 * @hw: pointer to the HW structure
1156 s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw)
1163 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1168 hw->mac.ops.config_collision_dist(hw);
1170 ret_val = e1000_commit_fc_settings_generic(hw);
1182 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1183 E1000_WRITE_FLUSH(hw);
1190 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1191 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {
1192 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
1202 * @hw: pointer to the HW structure
1207 static void e1000_config_collision_dist_generic(struct e1000_hw *hw)
1213 tctl = E1000_READ_REG(hw, E1000_TCTL);
1218 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1219 E1000_WRITE_FLUSH(hw);
1224 * @hw: pointer to the HW structure
1230 s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw)
1242 if (hw->fc.current_mode & e1000_fc_tx_pause) {
1247 fcrtl = hw->fc.low_water;
1248 if (hw->fc.send_xon)
1251 fcrth = hw->fc.high_water;
1253 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl);
1254 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth);
1261 * @hw: pointer to the HW structure
1269 s32 e1000_force_mac_fc_generic(struct e1000_hw *hw)
1275 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1283 * according to the "hw->fc.current_mode" parameter.
1294 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode);
1296 switch (hw->fc.current_mode) {
1316 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1323 * @hw: pointer to the HW structure
1331 s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw)
1333 struct e1000_mac_info *mac = &hw->mac;
1346 if (hw->phy.media_type == e1000_media_type_fiber ||
1347 hw->phy.media_type == e1000_media_type_internal_serdes)
1348 ret_val = e1000_force_mac_fc_generic(hw);
1350 if (hw->phy.media_type == e1000_media_type_copper)
1351 ret_val = e1000_force_mac_fc_generic(hw);
1364 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1369 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1372 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1387 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
1391 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
1437 if (hw->fc.requested_mode == e1000_fc_full) {
1438 hw->fc.current_mode = e1000_fc_full;
1441 hw->fc.current_mode = e1000_fc_rx_pause;
1456 hw->fc.current_mode = e1000_fc_tx_pause;
1470 hw->fc.current_mode = e1000_fc_rx_pause;
1476 hw->fc.current_mode = e1000_fc_none;
1484 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1491 hw->fc.current_mode = e1000_fc_none;
1496 ret_val = e1000_force_mac_fc_generic(hw);
1508 if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
1513 pcs_status_reg = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1526 pcs_adv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1527 pcs_lp_ability_reg = E1000_READ_REG(hw, E1000_PCS_LPAB);
1570 if (hw->fc.requested_mode == e1000_fc_full) {
1571 hw->fc.current_mode = e1000_fc_full;
1574 hw->fc.current_mode = e1000_fc_rx_pause;
1589 hw->fc.current_mode = e1000_fc_tx_pause;
1603 hw->fc.current_mode = e1000_fc_rx_pause;
1609 hw->fc.current_mode = e1000_fc_none;
1616 pcs_ctrl_reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1618 E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_ctrl_reg);
1620 ret_val = e1000_force_mac_fc_generic(hw);
1632 * @hw: pointer to the HW structure
1639 s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,
1646 status = E1000_READ_REG(hw, E1000_STATUS);
1671 * @hw: pointer to the HW structure
1678 s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw,
1691 * @hw: pointer to the HW structure
1695 s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw)
1698 s32 timeout = hw->nvm.word_size + 1;
1705 swsm = E1000_READ_REG(hw, E1000_SWSM);
1720 swsm = E1000_READ_REG(hw, E1000_SWSM);
1721 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
1724 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
1732 e1000_put_hw_semaphore_generic(hw);
1742 * @hw: pointer to the HW structure
1746 void e1000_put_hw_semaphore_generic(struct e1000_hw *hw)
1752 swsm = E1000_READ_REG(hw, E1000_SWSM);
1756 E1000_WRITE_REG(hw, E1000_SWSM, swsm);
1761 * @hw: pointer to the HW structure
1765 s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw)
1772 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD)
1788 * @hw: pointer to the HW structure
1794 s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data)
1800 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1814 * @hw: pointer to the HW structure
1817 s32 e1000_id_led_init_generic(struct e1000_hw *hw)
1819 struct e1000_mac_info *mac = &hw->mac;
1829 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1833 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
1880 * @hw: pointer to the HW structure
1885 s32 e1000_setup_led_generic(struct e1000_hw *hw)
1891 if (hw->mac.ops.setup_led != e1000_setup_led_generic)
1894 if (hw->phy.media_type == e1000_media_type_fiber) {
1895 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
1896 hw->mac.ledctl_default = ledctl;
1902 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
1903 } else if (hw->phy.media_type == e1000_media_type_copper) {
1904 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1912 * @hw: pointer to the HW structure
1917 s32 e1000_cleanup_led_generic(struct e1000_hw *hw)
1921 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1927 * @hw: pointer to the HW structure
1931 s32 e1000_blink_led_generic(struct e1000_hw *hw)
1938 if (hw->phy.media_type == e1000_media_type_fiber) {
1949 ledctl_blink = hw->mac.ledctl_mode2;
1951 u32 mode = (hw->mac.ledctl_mode2 >> i) &
1953 u32 led_default = hw->mac.ledctl_default >> i;
1967 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink);
1974 * @hw: pointer to the HW structure
1978 s32 e1000_led_on_generic(struct e1000_hw *hw)
1984 switch (hw->phy.media_type) {
1986 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1989 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1992 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
2003 * @hw: pointer to the HW structure
2007 s32 e1000_led_off_generic(struct e1000_hw *hw)
2013 switch (hw->phy.media_type) {
2015 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2018 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2021 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
2032 * @hw: pointer to the HW structure
2037 void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop)
2043 if (hw->bus.type != e1000_bus_type_pci_express)
2047 gcr = E1000_READ_REG(hw, E1000_GCR);
2050 E1000_WRITE_REG(hw, E1000_GCR, gcr);
2056 * @hw: pointer to the HW structure
2065 s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw)
2072 if (hw->bus.type != e1000_bus_type_pci_express)
2075 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2077 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2080 if (!(E1000_READ_REG(hw, E1000_STATUS) &
2097 * @hw: pointer to the HW structure
2101 void e1000_reset_adaptive_generic(struct e1000_hw *hw)
2103 struct e1000_mac_info *mac = &hw->mac;
2119 E1000_WRITE_REG(hw, E1000_AIT, 0);
2124 * @hw: pointer to the HW structure
2129 void e1000_update_adaptive_generic(struct e1000_hw *hw)
2131 struct e1000_mac_info *mac = &hw->mac;
2149 E1000_WRITE_REG(hw, E1000_AIT,
2158 E1000_WRITE_REG(hw, E1000_AIT, 0);
2165 * @hw: pointer to the HW structure
2170 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw)
2174 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
2176 hw->phy.mdix = 1;
2185 * @hw: pointer to the HW structure
2190 s32 e1000_validate_mdi_setting_crossover_generic(struct e1000_hw *hw)
2199 * @hw: pointer to the HW structure
2208 s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,
2217 E1000_WRITE_REG(hw, reg, regvalue);
2222 regvalue = E1000_READ_REG(hw, reg);