Lines Matching refs:phy_data
1640 u16 phy_data;
1648 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
1652 phy_data &= ~HV_SMB_ADDR_MASK;
1653 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
1654 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
1659 phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
1660 phy_data |= (freq & (1 << 0)) <<
1662 phy_data |= (freq & (1 << 1)) <<
1669 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2031 u16 phy_data;
2093 ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2097 phy_data & 0x00FF);
4878 u16 phy_data;
4911 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4912 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4913 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4914 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4915 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4916 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4917 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4918 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4919 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4920 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4921 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4922 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4923 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4924 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);