Lines Matching refs:hw
66 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
67 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
68 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
69 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
70 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
71 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
72 static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
73 static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
74 static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
77 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
78 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
79 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
80 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
82 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
84 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
86 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
88 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
89 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
90 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
92 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
93 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
94 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw);
95 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);
96 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
97 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
98 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
99 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
101 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
102 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
103 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
104 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
105 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
106 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
107 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
108 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
109 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
110 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
111 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
112 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
113 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
115 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
117 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
119 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
121 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
122 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
123 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
124 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
125 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
126 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
127 static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr);
172 * @hw: pointer to the HW structure
178 * Assumes the sw/fw/hw semaphore is already acquired.
180 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
188 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
193 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
202 if (hw->phy.id) {
203 if (hw->phy.id == phy_id)
206 hw->phy.id = phy_id;
207 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
214 hw->phy.ops.release(hw);
215 ret_val = e1000_set_mdio_slow_mode_hv(hw);
217 ret_val = e1000_get_phy_id(hw);
218 hw->phy.ops.acquire(hw);
225 * @hw: pointer to the HW structure
230 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
232 u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);
241 e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
243 ret_val = hw->phy.ops.acquire(hw);
253 switch (hw->mac.type) {
255 if (e1000_phy_is_accessible_pchlan(hw))
261 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
263 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
267 if (e1000_phy_is_accessible_pchlan(hw)) {
268 if (hw->mac.type == e1000_pch_lpt) {
270 hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL,
273 hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL,
277 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
279 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
286 if ((hw->mac.type == e1000_pchlan) &&
290 if (hw->phy.ops.check_reset_block(hw)) {
298 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
301 E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);
303 if (hw->mac.type == e1000_pch_lpt) {
307 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
309 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
313 mac_reg = E1000_READ_REG(hw, E1000_CTRL);
316 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
317 E1000_WRITE_FLUSH(hw);
320 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
321 E1000_WRITE_FLUSH(hw);
322 if (hw->mac.type < e1000_pch_lpt) {
328 } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) &
336 hw->phy.ops.release(hw);
343 ret_val = e1000_phy_hw_reset_generic(hw);
347 if ((hw->mac.type == e1000_pch2lan) &&
350 e1000_gate_hw_phy_config_ich8lan(hw, FALSE);
358 * @hw: pointer to the HW structure
362 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
364 struct e1000_phy_info *phy = &hw->phy;
392 ret_val = e1000_init_phy_workarounds_pchlan(hw);
397 switch (hw->mac.type) {
399 ret_val = e1000_get_phy_id(hw);
410 ret_val = e1000_set_mdio_slow_mode_hv(hw);
413 ret_val = e1000_get_phy_id(hw);
447 * @hw: pointer to the HW structure
451 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
453 struct e1000_phy_info *phy = &hw->phy;
478 ret_val = e1000_determine_phy_address(hw);
482 ret_val = e1000_determine_phy_address(hw);
493 ret_val = e1000_get_phy_id(hw);
538 * @hw: pointer to the HW structure
543 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
545 struct e1000_nvm_info *nvm = &hw->nvm;
546 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
553 if (!hw->flash_address) {
560 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
606 * @hw: pointer to the HW structure
611 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
613 struct e1000_mac_info *mac = &hw->mac;
618 hw->phy.media_type = e1000_media_type_copper;
643 /* hw initialization */
711 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE);
718 * @hw: pointer to the HW structure
725 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
732 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
737 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
740 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
748 * @hw: pointer to the HW structure
754 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
758 return __e1000_access_emi_reg_locked(hw, addr, data, TRUE);
763 * @hw: pointer to the HW structure
769 static s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
773 return __e1000_access_emi_reg_locked(hw, addr, &data, FALSE);
778 * @hw: pointer to the HW structure
784 static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
786 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
792 if ((hw->phy.type != e1000_phy_82579) &&
793 (hw->phy.type != e1000_phy_i217))
796 ret_val = hw->phy.ops.acquire(hw);
800 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
812 switch (hw->phy.type) {
825 ret_val = e1000_read_emi_reg_locked(hw, lpa,
837 hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);
850 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
855 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
857 hw->phy.ops.release(hw);
864 * @hw: pointer to the HW structure
871 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
873 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
876 if (link && (E1000_READ_REG(hw, E1000_STATUS) &
880 ret_val = hw->phy.ops.acquire(hw);
885 e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
891 e1000_write_kmrn_reg_locked(hw,
900 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
904 e1000_write_kmrn_reg_locked(hw,
908 hw->phy.ops.release(hw);
911 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
931 * @hw: pointer to the HW structure
948 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
965 if (!hw->mac.max_frame_size) {
970 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
977 rxa = E1000_READ_REG(hw, E1000_PBA) & E1000_PBA_RXA_MASK;
988 (2 * (s64)hw->mac.max_frame_size)) * 8 * 1000;
1006 e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT, &max_snoop);
1007 e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
1030 E1000_WRITE_REG(hw, E1000_LTRV, reg);
1033 reg = E1000_READ_REG(hw, E1000_SVT) & ~E1000_SVT_OFF_HWM_MASK;
1035 E1000_WRITE_REG(hw, E1000_SVT, reg);
1038 reg = E1000_READ_REG(hw, E1000_SVCR);
1045 E1000_WRITE_REG(hw, E1000_SVCR, reg);
1052 * @hw: pointer to the HW structure
1057 static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr)
1073 svcr = E1000_READ_REG(hw, E1000_SVCR);
1076 E1000_WRITE_REG(hw, E1000_SVCR, svcr);
1083 * @hw: pointer to the HW structure
1089 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1091 struct e1000_mac_info *mac = &hw->mac;
1110 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1114 if (hw->mac.type == e1000_pchlan) {
1115 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1124 if ((hw->mac.type == e1000_pch2lan) && link) {
1126 reg = E1000_READ_REG(hw, E1000_STATUS);
1128 reg = E1000_READ_REG(hw, E1000_TIPG);
1131 E1000_WRITE_REG(hw, E1000_TIPG, reg);
1134 ret_val = hw->phy.ops.acquire(hw);
1138 ret_val = e1000_write_emi_reg_locked(hw, I82579_RX_CONFIG, 0);
1140 hw->phy.ops.release(hw);
1148 if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1149 (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V)) {
1150 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1155 if (hw->mac.type == e1000_pch_lpt) {
1159 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1165 hw->dev_spec.ich8lan.eee_lp_ability = 0;
1172 switch (hw->mac.type) {
1174 ret_val = e1000_k1_workaround_lv(hw);
1179 if (hw->phy.type == e1000_phy_82578) {
1180 ret_val = e1000_link_stall_workaround_hv(hw);
1190 hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1193 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) !=
1197 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1206 e1000_check_downshift_generic(hw);
1209 ret_val = e1000_set_eee_pchlan(hw);
1223 mac->ops.config_collision_dist(hw);
1230 ret_val = e1000_config_fc_after_link_up_generic(hw);
1239 * @hw: pointer to the HW structure
1243 void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
1247 hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
1248 hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
1249 switch (hw->mac.type) {
1253 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
1258 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
1267 * @hw: pointer to the HW structure
1271 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
1275 E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1282 * @hw: pointer to the HW structure
1286 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
1290 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1297 * @hw: pointer to the HW structure
1302 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1309 E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1312 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1329 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1332 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1342 E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl);
1344 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1351 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1358 * @hw: pointer to the HW structure
1363 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1369 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1373 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1375 DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n");
1378 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1385 * @hw: pointer to the HW structure
1391 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1397 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1406 * @hw: pointer to the HW structure
1412 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1418 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1426 * @hw: pointer to the HW structure
1435 static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1455 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
1456 E1000_WRITE_FLUSH(hw);
1457 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
1458 E1000_WRITE_FLUSH(hw);
1462 if (index < hw->mac.rar_entry_count) {
1465 ret_val = e1000_acquire_swflag_ich8lan(hw);
1469 E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low);
1470 E1000_WRITE_FLUSH(hw);
1471 E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high);
1472 E1000_WRITE_FLUSH(hw);
1474 e1000_release_swflag_ich8lan(hw);
1477 if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) &&
1478 (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high))
1482 (index - 1), E1000_READ_REG(hw, E1000_FWSM));
1491 * @hw: pointer to the HW structure
1500 static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1520 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
1521 E1000_WRITE_FLUSH(hw);
1522 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
1523 E1000_WRITE_FLUSH(hw);
1530 if (index < hw->mac.rar_entry_count) {
1531 wlock_mac = E1000_READ_REG(hw, E1000_FWSM) &
1542 ret_val = e1000_acquire_swflag_ich8lan(hw);
1547 E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1),
1549 E1000_WRITE_FLUSH(hw);
1550 E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1),
1552 E1000_WRITE_FLUSH(hw);
1554 e1000_release_swflag_ich8lan(hw);
1557 if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) &&
1558 (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high))
1569 * @hw: pointer to the HW structure
1576 static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
1586 e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count);
1588 ret_val = hw->phy.ops.acquire(hw);
1592 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1596 for (i = 0; i < hw->mac.mta_reg_count; i++) {
1597 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
1598 (u16)(hw->mac.mta_shadow[i] &
1600 hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1),
1601 (u16)((hw->mac.mta_shadow[i] >> 16) &
1605 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1608 hw->phy.ops.release(hw);
1613 * @hw: pointer to the HW structure
1619 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
1625 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1633 * @hw: pointer to the HW structure
1638 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
1641 u32 strap = E1000_READ_REG(hw, E1000_STRAP);
1648 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
1656 if (hw->phy.type == e1000_phy_i217) {
1669 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
1674 * @hw: pointer to the HW structure
1679 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
1681 struct e1000_phy_info *phy = &hw->phy;
1694 switch (hw->mac.type) {
1699 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) ||
1700 (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {
1714 ret_val = hw->phy.ops.acquire(hw);
1718 data = E1000_READ_REG(hw, E1000_FEXTNVM);
1725 data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1726 if ((hw->mac.type < e1000_pch2lan) &&
1730 cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
1739 if (((hw->mac.type == e1000_pchlan) &&
1741 (hw->mac.type > e1000_pchlan)) {
1747 ret_val = e1000_write_smbus_addr(hw);
1751 data = E1000_READ_REG(hw, E1000_LEDCTL);
1752 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1764 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
1769 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
1783 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
1790 hw->phy.ops.release(hw);
1796 * @hw: pointer to the HW structure
1804 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1808 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1812 if (hw->mac.type != e1000_pchlan)
1816 ret_val = hw->phy.ops.acquire(hw);
1822 if (hw->phy.type == e1000_phy_82578) {
1823 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
1838 if (hw->phy.type == e1000_phy_82577) {
1839 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
1855 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1862 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1868 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1871 hw->phy.ops.release(hw);
1878 * @hw: pointer to the HW structure
1886 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1896 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1906 ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1912 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1913 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1917 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1919 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1920 E1000_WRITE_FLUSH(hw);
1922 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1923 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1924 E1000_WRITE_FLUSH(hw);
1932 * @hw: pointer to the HW structure
1939 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1947 if (hw->mac.type < e1000_pchlan)
1950 ret_val = hw->phy.ops.acquire(hw);
1954 if (hw->mac.type == e1000_pchlan) {
1955 mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1960 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM);
1964 mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
1966 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1989 if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
1990 !hw->phy.ops.check_reset_block(hw))
1993 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1996 hw->phy.ops.release(hw);
2004 * @hw: pointer to the HW structure
2006 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2013 ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);
2019 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);
2028 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2035 if (hw->mac.type != e1000_pchlan)
2039 if (hw->phy.type == e1000_phy_82577) {
2040 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2045 if (((hw->phy.type == e1000_phy_82577) &&
2046 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2047 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2049 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
2054 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
2060 if (hw->phy.type == e1000_phy_82578) {
2064 if (hw->phy.revision < 2) {
2065 e1000_phy_sw_reset_generic(hw);
2066 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
2072 ret_val = hw->phy.ops.acquire(hw);
2076 hw->phy.addr = 1;
2077 ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2078 hw->phy.ops.release(hw);
2085 ret_val = e1000_k1_gig_workaround_hv(hw, TRUE);
2090 ret_val = hw->phy.ops.acquire(hw);
2093 ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2096 ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
2102 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2104 hw->phy.ops.release(hw);
2111 * @hw: pointer to the HW structure
2113 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2121 ret_val = hw->phy.ops.acquire(hw);
2124 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2129 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
2130 mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
2131 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2133 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2136 mac_reg = E1000_READ_REG(hw, E1000_RAH(i));
2137 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2139 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2144 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2147 hw->phy.ops.release(hw);
2171 * @hw: pointer to the HW structure
2174 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2183 if (hw->mac.type < e1000_pch2lan)
2187 hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
2188 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
2197 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
2201 addr_high = E1000_READ_REG(hw, E1000_RAH(i));
2204 addr_low = E1000_READ_REG(hw, E1000_RAL(i));
2212 E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2217 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2220 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2223 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2225 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2227 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2229 ret_val = e1000_read_kmrn_reg_generic(hw,
2234 ret_val = e1000_write_kmrn_reg_generic(hw,
2239 ret_val = e1000_read_kmrn_reg_generic(hw,
2246 ret_val = e1000_write_kmrn_reg_generic(hw,
2253 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2256 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2259 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2261 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2264 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2267 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2270 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
2273 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2274 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
2280 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2282 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2284 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2286 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2288 ret_val = e1000_read_kmrn_reg_generic(hw,
2293 ret_val = e1000_write_kmrn_reg_generic(hw,
2298 ret_val = e1000_read_kmrn_reg_generic(hw,
2305 ret_val = e1000_write_kmrn_reg_generic(hw,
2312 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2314 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2317 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2319 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2322 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2325 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2328 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
2331 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2332 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
2339 return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
2347 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2353 if (hw->mac.type != e1000_pch2lan)
2357 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2361 ret_val = hw->phy.ops.acquire(hw);
2365 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2369 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2371 hw->phy.ops.release(hw);
2378 * @hw: pointer to the HW structure
2382 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2391 if (hw->mac.type != e1000_pch2lan)
2395 ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
2401 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
2404 ret_val = hw->phy.ops.read_reg(hw, I82579_LPI_CTRL, &phy_reg);
2414 ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
2419 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
2427 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
2428 ret_val = hw->phy.ops.write_reg(hw, I82579_LPI_CTRL, phy_reg);
2436 * @hw: pointer to the HW structure
2442 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2448 if (hw->mac.type < e1000_pch2lan)
2451 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2458 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
2463 * @hw: pointer to the HW structure
2468 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2476 data = E1000_READ_REG(hw, E1000_STATUS);
2489 data = E1000_READ_REG(hw, E1000_STATUS);
2491 E1000_WRITE_REG(hw, E1000_STATUS, data);
2496 * @hw: pointer to the HW structure
2498 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2505 if (hw->phy.ops.check_reset_block(hw))
2512 switch (hw->mac.type) {
2514 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2519 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2528 if (hw->mac.type >= e1000_pchlan) {
2529 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, ®);
2531 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);
2535 ret_val = e1000_sw_lcd_config_ich8lan(hw);
2540 ret_val = e1000_oem_bits_config_ich8lan(hw, TRUE);
2542 if (hw->mac.type == e1000_pch2lan) {
2544 if (!(E1000_READ_REG(hw, E1000_FWSM) &
2547 e1000_gate_hw_phy_config_ich8lan(hw, FALSE);
2551 ret_val = hw->phy.ops.acquire(hw);
2554 ret_val = e1000_write_emi_reg_locked(hw,
2557 hw->phy.ops.release(hw);
2565 * @hw: pointer to the HW structure
2571 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2578 if ((hw->mac.type == e1000_pch2lan) &&
2579 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
2580 e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
2582 ret_val = e1000_phy_hw_reset_generic(hw);
2586 return e1000_post_phy_reset_ich8lan(hw);
2591 * @hw: pointer to the HW structure
2597 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
2600 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2607 ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
2616 if (!hw->phy.ops.check_reset_block(hw))
2619 return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
2624 * @hw: pointer to the HW structure
2635 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2637 struct e1000_phy_info *phy = &hw->phy;
2647 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
2651 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
2659 if (hw->mac.type == e1000_ich8lan)
2660 e1000_gig_downshift_workaround_ich8lan(hw);
2663 ret_val = phy->ops.read_reg(hw,
2669 ret_val = phy->ops.write_reg(hw,
2676 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
2687 ret_val = phy->ops.read_reg(hw,
2694 ret_val = phy->ops.write_reg(hw,
2700 ret_val = phy->ops.read_reg(hw,
2707 ret_val = phy->ops.write_reg(hw,
2720 * @hw: pointer to the HW structure
2731 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2733 struct e1000_phy_info *phy = &hw->phy;
2740 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
2744 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
2755 ret_val = phy->ops.read_reg(hw,
2762 ret_val = phy->ops.write_reg(hw,
2768 ret_val = phy->ops.read_reg(hw,
2775 ret_val = phy->ops.write_reg(hw,
2785 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
2793 if (hw->mac.type == e1000_ich8lan)
2794 e1000_gig_downshift_workaround_ich8lan(hw);
2797 ret_val = phy->ops.read_reg(hw,
2804 ret_val = phy->ops.write_reg(hw,
2814 * @hw: pointer to the HW structure
2820 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
2823 struct e1000_nvm_info *nvm = &hw->nvm;
2831 switch (hw->mac.type) {
2834 eecd = E1000_READ_REG(hw, E1000_EECD);
2851 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
2862 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
2880 * @hw: pointer to the HW structure
2887 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2890 struct e1000_nvm_info *nvm = &hw->nvm;
2891 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2906 nvm->ops.acquire(hw);
2908 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2922 ret_val = e1000_read_flash_word_ich8lan(hw,
2931 nvm->ops.release(hw);
2942 * @hw: pointer to the HW structure
2947 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2954 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
2962 /* Clear FCERR and DAEL in hw status by writing 1 */
2966 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
2982 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
2991 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3004 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3016 * @hw: pointer to the HW structure
3021 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3030 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3032 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3036 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3050 * @hw: pointer to the HW structure
3057 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3068 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3073 * @hw: pointer to the HW structure
3079 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3085 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3096 * @hw: pointer to the HW structure
3103 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3119 hw->nvm.flash_base_addr;
3124 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3128 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3132 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3134 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3136 ret_val = e1000_flash_cycle_ich8lan(hw,
3145 flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3157 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3174 * @hw: pointer to the HW structure
3181 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3184 struct e1000_nvm_info *nvm = &hw->nvm;
3185 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3196 nvm->ops.acquire(hw);
3203 nvm->ops.release(hw);
3210 * @hw: pointer to the HW structure
3219 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3221 struct e1000_nvm_info *nvm = &hw->nvm;
3222 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3229 ret_val = e1000_update_nvm_checksum_generic(hw);
3236 nvm->ops.acquire(hw);
3242 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3251 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3257 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3270 ret_val = e1000_read_flash_word_ich8lan(hw, i +
3292 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3299 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3320 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
3325 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3337 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
3348 nvm->ops.release(hw);
3354 nvm->ops.reload(hw);
3367 * @hw: pointer to the HW structure
3373 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
3387 switch (hw->mac.type) {
3398 ret_val = hw->nvm.ops.read(hw, word, 1, &data);
3404 ret_val = hw->nvm.ops.write(hw, word, 1, &data);
3407 ret_val = hw->nvm.ops.update(hw);
3412 return e1000_validate_nvm_checksum_generic(hw);
3417 * @hw: pointer to the HW structure
3424 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3441 hw->nvm.flash_base_addr;
3446 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3450 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3454 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3456 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3463 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
3468 ret_val = e1000_flash_cycle_ich8lan(hw,
3478 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3493 * @hw: pointer to the HW structure
3499 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3506 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
3511 * @hw: pointer to the HW structure
3518 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
3526 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3533 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3545 * @hw: pointer to the HW structure
3551 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
3553 struct e1000_nvm_info *nvm = &hw->nvm;
3565 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3567 /* Determine HW Sector size: Read BERASE bits of hw flash status
3602 flash_linear_addr = hw->nvm.flash_base_addr;
3608 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3613 * Cycle field in hw flash control
3615 hsflctl.regval = E1000_READ_FLASH_REG16(hw,
3618 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
3626 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
3629 ret_val = e1000_flash_cycle_ich8lan(hw,
3638 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3653 * @hw: pointer to the HW structure
3660 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
3666 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
3680 * @hw: pointer to the HW structure
3691 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
3693 struct e1000_mac_info *mac = &hw->mac;
3702 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
3706 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
3754 * @hw: pointer to the HW structure
3759 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
3761 struct e1000_bus_info *bus = &hw->bus;
3766 ret_val = e1000_get_bus_info_pcie_generic(hw);
3781 * @hw: pointer to the HW structure
3786 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
3788 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3798 ret_val = e1000_disable_pcie_master_generic(hw);
3803 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
3809 E1000_WRITE_REG(hw, E1000_RCTL, 0);
3810 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
3811 E1000_WRITE_FLUSH(hw);
3816 if (hw->mac.type == e1000_ich8lan) {
3818 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
3820 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
3823 if (hw->mac.type == e1000_pchlan) {
3825 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
3835 ctrl = E1000_READ_REG(hw, E1000_CTRL);
3837 if (!hw->phy.ops.check_reset_block(hw)) {
3847 if ((hw->mac.type == e1000_pch2lan) &&
3848 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
3849 e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
3851 ret_val = e1000_acquire_swflag_ich8lan(hw);
3853 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
3858 if (hw->mac.type == e1000_pch2lan) {
3859 reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
3862 E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg);
3866 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
3869 ret_val = hw->phy.ops.get_cfg_done(hw);
3873 ret_val = e1000_post_phy_reset_ich8lan(hw);
3882 if (hw->mac.type == e1000_pchlan)
3883 E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565);
3885 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
3886 E1000_READ_REG(hw, E1000_ICR);
3888 reg = E1000_READ_REG(hw, E1000_KABGTXD);
3890 E1000_WRITE_REG(hw, E1000_KABGTXD, reg);
3897 * @hw: pointer to the HW structure
3907 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3909 struct e1000_mac_info *mac = &hw->mac;
3916 e1000_initialize_hw_bits_ich8lan(hw);
3919 ret_val = mac->ops.id_led_init(hw);
3925 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
3930 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3936 if (hw->phy.type == e1000_phy_82578) {
3937 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i);
3939 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i);
3940 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3946 ret_val = mac->ops.setup_link(hw);
3949 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
3954 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
3955 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
3960 E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
3969 e1000_set_pcie_no_snoop_generic(hw, snoop);
3971 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
3973 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3980 e1000_clear_hw_cntrs_ich8lan(hw);
3987 * @hw: pointer to the HW structure
3992 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3999 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
4002 if (hw->mac.type >= e1000_pchlan)
4004 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
4007 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
4009 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
4012 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
4014 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
4017 reg = E1000_READ_REG(hw, E1000_TARC(0));
4018 if (hw->mac.type == e1000_ich8lan)
4021 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
4024 reg = E1000_READ_REG(hw, E1000_TARC(1));
4025 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
4030 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
4033 if (hw->mac.type == e1000_ich8lan) {
4034 reg = E1000_READ_REG(hw, E1000_STATUS);
4036 E1000_WRITE_REG(hw, E1000_STATUS, reg);
4042 reg = E1000_READ_REG(hw, E1000_RFCTL);
4047 if (hw->mac.type == e1000_ich8lan)
4049 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
4052 if (hw->mac.type == e1000_pch_lpt) {
4053 reg = E1000_READ_REG(hw, E1000_PBECCSTS);
4055 E1000_WRITE_REG(hw, E1000_PBECCSTS, reg);
4057 reg = E1000_READ_REG(hw, E1000_CTRL);
4059 E1000_WRITE_REG(hw, E1000_CTRL, reg);
4067 * @hw: pointer to the HW structure
4075 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
4081 if (hw->phy.ops.check_reset_block(hw))
4088 if (hw->fc.requested_mode == e1000_fc_default)
4089 hw->fc.requested_mode = e1000_fc_full;
4094 hw->fc.current_mode = hw->fc.requested_mode;
4097 hw->fc.current_mode);
4100 ret_val = hw->mac.ops.setup_physical_interface(hw);
4104 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
4105 if ((hw->phy.type == e1000_phy_82578) ||
4106 (hw->phy.type == e1000_phy_82579) ||
4107 (hw->phy.type == e1000_phy_i217) ||
4108 (hw->phy.type == e1000_phy_82577)) {
4109 E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time);
4111 ret_val = hw->phy.ops.write_reg(hw,
4113 hw->fc.pause_time);
4118 return e1000_set_fc_watermarks_generic(hw);
4123 * @hw: pointer to the HW structure
4129 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
4137 ctrl = E1000_READ_REG(hw, E1000_CTRL);
4140 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
4146 ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
4150 ret_val = e1000_read_kmrn_reg_generic(hw,
4156 ret_val = e1000_write_kmrn_reg_generic(hw,
4162 switch (hw->phy.type) {
4164 ret_val = e1000_copper_link_setup_igp(hw);
4170 ret_val = e1000_copper_link_setup_m88(hw);
4176 ret_val = e1000_copper_link_setup_82577(hw);
4181 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
4188 switch (hw->phy.mdix) {
4200 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
4209 return e1000_setup_copper_link_generic(hw);
4214 * @hw: pointer to the HW structure
4220 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
4227 ctrl = E1000_READ_REG(hw, E1000_CTRL);
4230 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
4232 ret_val = e1000_copper_link_setup_82577(hw);
4236 return e1000_setup_copper_link_generic(hw);
4241 * @hw: pointer to the HW structure
4249 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
4256 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
4260 if ((hw->mac.type == e1000_ich8lan) &&
4261 (hw->phy.type == e1000_phy_igp_3) &&
4263 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
4271 * @hw: pointer to the HW structure
4284 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
4286 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4301 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
4307 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
4311 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
4320 hw->phy.ops.reset(hw);
4324 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
4327 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
4332 e1000_gig_downshift_workaround_ich8lan(hw);
4340 * @hw: pointer to the HW structure
4346 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
4349 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4353 if (hw->mac.type != e1000_ich8lan) {
4365 * @hw: pointer to the HW structure
4373 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
4381 if (hw->phy.type != e1000_phy_igp_3)
4387 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
4390 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
4395 if (hw->mac.type == e1000_ich8lan)
4396 e1000_gig_downshift_workaround_ich8lan(hw);
4399 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
4401 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
4405 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
4411 reg = E1000_READ_REG(hw, E1000_CTRL);
4412 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
4419 * @hw: pointer to the HW structure
4427 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
4434 if ((hw->mac.type != e1000_ich8lan) ||
4435 (hw->phy.type == e1000_phy_ife))
4438 ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4443 ret_val = e1000_write_kmrn_reg_generic(hw,
4449 e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4455 * @hw: pointer to the HW structure
4467 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
4469 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4475 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
4478 if (hw->phy.type == e1000_phy_i217) {
4479 u16 phy_reg, device_id = hw->device_id;
4483 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
4485 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
4489 ret_val = hw->phy.ops.acquire(hw);
4497 e1000_read_emi_reg_locked(hw,
4510 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL))
4522 if (!(E1000_READ_REG(hw, E1000_FWSM) &
4525 hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL,
4528 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL,
4534 hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg);
4536 hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg);
4539 hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg);
4541 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
4547 hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg);
4549 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
4552 hw->phy.ops.release(hw);
4555 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
4557 if (hw->mac.type == e1000_ich8lan)
4558 e1000_gig_downshift_workaround_ich8lan(hw);
4560 if (hw->mac.type >= e1000_pchlan) {
4561 e1000_oem_bits_config_ich8lan(hw, FALSE);
4564 if (hw->mac.type == e1000_pchlan)
4565 e1000_phy_hw_reset_generic(hw);
4567 ret_val = hw->phy.ops.acquire(hw);
4570 e1000_write_smbus_addr(hw);
4571 hw->phy.ops.release(hw);
4579 * @hw: pointer to the HW structure
4587 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
4593 if (hw->mac.type < e1000_pch2lan)
4596 ret_val = e1000_init_phy_workarounds_pchlan(hw);
4607 if (hw->phy.type == e1000_phy_i217) {
4610 ret_val = hw->phy.ops.acquire(hw);
4616 if (!(E1000_READ_REG(hw, E1000_FWSM) &
4621 ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,
4626 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
4629 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0);
4632 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,
4637 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
4641 hw->phy.ops.release(hw);
4647 * @hw: pointer to the HW structure
4651 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
4655 if (hw->phy.type == e1000_phy_ife)
4656 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4659 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
4665 * @hw: pointer to the HW structure
4669 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
4673 if (hw->phy.type == e1000_phy_ife)
4674 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4677 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
4683 * @hw: pointer to the HW structure
4687 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
4691 if (hw->phy.type == e1000_phy_ife)
4692 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4695 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
4701 * @hw: pointer to the HW structure
4705 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
4709 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
4710 (u16)hw->mac.ledctl_mode1);
4715 * @hw: pointer to the HW structure
4719 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
4723 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
4724 (u16)hw->mac.ledctl_default);
4729 * @hw: pointer to the HW structure
4733 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
4735 u16 data = (u16)hw->mac.ledctl_mode2;
4743 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
4756 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
4761 * @hw: pointer to the HW structure
4765 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
4767 u16 data = (u16)hw->mac.ledctl_mode1;
4775 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
4788 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
4793 * @hw: pointer to the HW structure
4803 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
4811 e1000_get_cfg_done_generic(hw);
4814 if (hw->mac.type >= e1000_ich10lan) {
4815 e1000_lan_init_done_ich8lan(hw);
4817 ret_val = e1000_get_auto_rd_done_generic(hw);
4829 status = E1000_READ_REG(hw, E1000_STATUS);
4831 E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA);
4836 if (hw->mac.type <= e1000_ich9lan) {
4837 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
4838 (hw->phy.type == e1000_phy_igp_3)) {
4839 e1000_phy_init_script_igp3(hw);
4842 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
4854 * @hw: pointer to the HW structure
4859 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
4862 if (!(hw->mac.ops.check_mng_mode(hw) ||
4863 hw->phy.ops.check_reset_block(hw)))
4864 e1000_power_down_phy_copper(hw);
4871 * @hw: pointer to the HW structure
4876 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
4883 e1000_clear_hw_cntrs_base_generic(hw);
4885 E1000_READ_REG(hw, E1000_ALGNERRC);
4886 E1000_READ_REG(hw, E1000_RXERRC);
4887 E1000_READ_REG(hw, E1000_TNCRS);
4888 E1000_READ_REG(hw, E1000_CEXTERR);
4889 E1000_READ_REG(hw, E1000_TSCTC);
4890 E1000_READ_REG(hw, E1000_TSCTFC);
4892 E1000_READ_REG(hw, E1000_MGTPRC);
4893 E1000_READ_REG(hw, E1000_MGTPDC);
4894 E1000_READ_REG(hw, E1000_MGTPTC);
4896 E1000_READ_REG(hw, E1000_IAC);
4897 E1000_READ_REG(hw, E1000_ICRXOC);
4900 if ((hw->phy.type == e1000_phy_82578) ||
4901 (hw->phy.type == e1000_phy_82579) ||
4902 (hw->phy.type == e1000_phy_i217) ||
4903 (hw->phy.type == e1000_phy_82577)) {
4904 ret_val = hw->phy.ops.acquire(hw);
4907 ret_val = hw->phy.ops.set_page(hw,
4911 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4912 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4913 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4914 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4915 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4916 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4917 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4918 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4919 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4920 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4921 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4922 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4923 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4924 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4926 hw->phy.ops.release(hw);