dev/e1000/e1000_82575.c

165 	s32 ret_val = E1000_SUCCESS;
225 	ret_val = e1000_get_phy_id_82575(hw);
276 		ret_val = -E1000_ERR_PHY;
281 	return ret_val;
554 	s32 ret_val = -E1000_ERR_PARAM;
563 	ret_val = hw->phy.ops.acquire(hw);
564 	if (ret_val)
567 	ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
572 	return ret_val;
587 	s32 ret_val = -E1000_ERR_PARAM;
596 	ret_val = hw->phy.ops.acquire(hw);
597 	if (ret_val)
600 	ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
605 	return ret_val;
618 	s32  ret_val = E1000_SUCCESS;
634 		ret_val = e1000_get_phy_id(hw);
655 			ret_val = -E1000_ERR_PHY;
659 		ret_val = e1000_get_phy_id(hw);
675 		ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
676 		if (ret_val == E1000_SUCCESS) {
694 		ret_val = -E1000_ERR_PHY;
696 		ret_val = e1000_get_phy_id(hw);
703 	return ret_val;
714 	s32 ret_val = E1000_SUCCESS;
732 	ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
733 	if (ret_val)
736 	ret_val = hw->phy.ops.commit(hw);
739 	return ret_val;
758 	s32 ret_val = E1000_SUCCESS;
766 	ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
767 	if (ret_val)
772 		ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
774 		if (ret_val)
778 		ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
781 		ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
783 		if (ret_val)
787 		ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
796 			ret_val = phy->ops.read_reg(hw,
799 			if (ret_val)
803 			ret_val = phy->ops.write_reg(hw,
806 			if (ret_val)
809 			ret_val = phy->ops.read_reg(hw,
812 			if (ret_val)
816 			ret_val = phy->ops.write_reg(hw,
819 			if (ret_val)
825 	return ret_val;
844 	s32 ret_val = E1000_SUCCESS;
872 	return ret_val;
892 	s32 ret_val = E1000_SUCCESS;
920 	return ret_val;
934 	s32 ret_val;
938 	ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
939 	if (ret_val)
967 	ret_val = e1000_acquire_nvm_generic(hw);
968 	if (ret_val)
972 	return ret_val;
1004 	s32 ret_val = E1000_SUCCESS;
1011 			ret_val = -E1000_ERR_SWFW_SYNC;
1030 		ret_val = -E1000_ERR_SWFW_SYNC;
1040 	return ret_val;
1080 	s32 ret_val = E1000_SUCCESS;
1105 	return ret_val;
1121 	s32 ret_val;
1126 		ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1129 		ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1132 	return ret_val;
1144 	s32 ret_val;
1150 		ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1165 		ret_val = e1000_config_fc_after_link_up_generic(hw);
1166 		if (ret_val)
1169 		ret_val = e1000_check_for_copper_link_generic(hw);
1172 	return ret_val;
1302 	s32 ret_val;
1310 	ret_val = e1000_disable_pcie_master_generic(hw);
1311 	if (ret_val)
1315 	ret_val = e1000_set_pcie_completion_timeout(hw);
1316 	if (ret_val)
1333 	ret_val = e1000_get_auto_rd_done_generic(hw);
1334 	if (ret_val) {
1352 	ret_val = e1000_check_alt_mac_addr_generic(hw);
1354 	return ret_val;
1366 	s32 ret_val;
1372 	ret_val = mac->ops.id_led_init(hw);
1373 	if (ret_val) {
1396 	ret_val = mac->ops.setup_link(hw);
1409 	return ret_val;
1423 	s32 ret_val;
1440 	ret_val = e1000_setup_serdes_link_82575(hw);
1441 	if (ret_val)
1448 		ret_val = hw->phy.ops.reset(hw);
1449 		if (ret_val) {
1462 			ret_val = e1000_copper_link_setup_m88_gen2(hw);
1465 			ret_val = e1000_copper_link_setup_m88(hw);
1470 		ret_val = e1000_copper_link_setup_igp(hw);
1473 		ret_val = e1000_copper_link_setup_82577(hw);
1476 		ret_val = -E1000_ERR_PHY;
1480 	if (ret_val)
1483 	ret_val = e1000_setup_copper_link_generic(hw);
1485 	return ret_val;
1501 	s32 ret_val = E1000_SUCCESS;
1508 		return ret_val;
1549 			ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1550 			if (ret_val) {
1552 				return ret_val;
1626 	return ret_val;
1643 	s32 ret_val = E1000_SUCCESS;
1674 		ret_val = e1000_set_sfp_media_type_82575(hw);
1675 		if ((ret_val != E1000_SUCCESS) ||
1708 	return ret_val;
1720 	s32 ret_val = E1000_ERR_CONFIG;
1736 		ret_val = e1000_read_sfp_data_byte(hw,
1739 		if (ret_val == E1000_SUCCESS)
1744 	if (ret_val != E1000_SUCCESS)
1747 	ret_val = e1000_read_sfp_data_byte(hw,
1750 	if (ret_val != E1000_SUCCESS)
1773 	ret_val = E1000_SUCCESS;
1777 	return ret_val;
1790 	s32 ret_val;
1794 	ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1795 	if (ret_val) {
1812 	return ret_val;
1873 	s32 ret_val = E1000_SUCCESS;
1882 	ret_val = e1000_check_alt_mac_addr_generic(hw);
1883 	if (ret_val)
1886 	ret_val = e1000_read_mac_addr_generic(hw);
1889 	return ret_val;
2087 	s32 ret_val = E1000_SUCCESS;
2108 	ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2110 	if (ret_val)
2115 	ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2122 	return ret_val;
2239 	s32 ret_val;
2243 	ret_val = hw->phy.ops.acquire(hw);
2244 	if (ret_val)
2247 	ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
2252 	return ret_val;
2265 	s32 ret_val;
2269 	ret_val = hw->phy.ops.acquire(hw);
2270 	if (ret_val)
2273 	ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2278 	return ret_val;
2291 	s32 ret_val = E1000_SUCCESS;
2302 	ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2305 	if (ret_val) {
2317 	return ret_val;
2329 	s32 ret_val = E1000_SUCCESS;
2350 	ret_val = e1000_disable_pcie_master_generic(hw);
2351 	if (ret_val)
2380 	ret_val = e1000_get_auto_rd_done_generic(hw);
2381 	if (ret_val) {
2401 	ret_val = e1000_reset_mdicnfg_82580(hw);
2402 	if (ret_val)
2406 	ret_val = e1000_check_alt_mac_addr_generic(hw);
2412 	return ret_val;
2427 	u16 ret_val = 0;
2430 		ret_val = e1000_82580_rxpbs_table[data];
2432 	return ret_val;
2446 	s32 ret_val = E1000_SUCCESS;
2453 		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2454 		if (ret_val) {
2463 		ret_val = -E1000_ERR_NVM;
2468 	return ret_val;
2483 	s32 ret_val;
2490 		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2491 		if (ret_val) {
2498 	ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2500 	if (ret_val)
2504 	return ret_val;
2517 	s32 ret_val = E1000_SUCCESS;
2524 	ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2525 	if (ret_val) {
2538 		ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2540 		if (ret_val != E1000_SUCCESS)
2545 	return ret_val;
2558 	s32 ret_val;
2564 	ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2565 	if (ret_val) {
2573 		ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2575 		if (ret_val) {
2583 		ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2584 		if (ret_val)
2589 	return ret_val;
2602 	s32 ret_val = E1000_SUCCESS;
2610 		ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2612 		if (ret_val != E1000_SUCCESS)
2617 	return ret_val;
2630 	s32 ret_val = E1000_SUCCESS;
2638 		ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2639 		if (ret_val != E1000_SUCCESS)
2644 	return ret_val;
2656 	s32 ret_val = E1000_SUCCESS;
2689 	return ret_val;
2750 	s32 ret_val = E1000_SUCCESS;
2767 	return ret_val;