Lines Matching refs:hw
48 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw);
49 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw);
50 static s32 e1000_acquire_phy_82575(struct e1000_hw *hw);
51 static void e1000_release_phy_82575(struct e1000_hw *hw);
52 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw);
53 static void e1000_release_nvm_82575(struct e1000_hw *hw);
54 static s32 e1000_check_for_link_82575(struct e1000_hw *hw);
55 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw);
56 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
58 static s32 e1000_init_hw_82575(struct e1000_hw *hw);
59 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
60 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
62 static s32 e1000_reset_hw_82575(struct e1000_hw *hw);
63 static s32 e1000_reset_hw_82580(struct e1000_hw *hw);
64 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw,
66 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw,
68 static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
70 static s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
72 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
74 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw);
75 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw);
76 static s32 e1000_get_media_type_82575(struct e1000_hw *hw);
77 static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
78 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
79 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
81 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
82 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
83 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
85 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw);
86 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
87 static bool e1000_sgmii_active_82575(struct e1000_hw *hw);
88 static s32 e1000_reset_init_script_82575(struct e1000_hw *hw);
89 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw);
90 static void e1000_config_collision_dist_82575(struct e1000_hw *hw);
91 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
92 static void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
93 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
94 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
95 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
96 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
97 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
98 static s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
100 static s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
102 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
103 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
104 static void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value);
105 static void e1000_clear_vfta_i350(struct e1000_hw *hw);
107 static void e1000_i2c_start(struct e1000_hw *hw);
108 static void e1000_i2c_stop(struct e1000_hw *hw);
109 static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
110 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
111 static s32 e1000_get_i2c_ack(struct e1000_hw *hw);
112 static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
113 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
114 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
115 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
116 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
127 * @hw: pointer to the HW structure
132 static bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
139 switch (hw->mac.type) {
142 reg = E1000_READ_REG(hw, E1000_MDIC);
149 reg = E1000_READ_REG(hw, E1000_MDICNFG);
160 * @hw: pointer to the HW structure
162 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
164 struct e1000_phy_info *phy = &hw->phy;
173 if (hw->phy.media_type != e1000_media_type_copper) {
190 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
192 if (e1000_sgmii_active_82575(hw)) {
200 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
201 e1000_reset_mdicnfg_82580(hw);
203 if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
207 switch (hw->mac.type) {
225 ret_val = e1000_get_phy_id_82575(hw);
286 * @hw: pointer to the HW structure
288 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
290 struct e1000_nvm_info *nvm = &hw->nvm;
291 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
311 if (hw->mac.type < e1000_i210) {
352 switch (hw->mac.type) {
370 * @hw: pointer to the HW structure
372 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
374 struct e1000_mac_info *mac = &hw->mac;
375 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
380 e1000_get_media_type_82575(hw);
384 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
408 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
419 /* hw initialization */
425 (hw->phy.media_type == e1000_media_type_copper)
450 if (hw->mac.type >= e1000_82580)
477 hw->mac.ops.set_lan_id(hw);
484 * @hw: pointer to the HW structure
488 void e1000_init_function_pointers_82575(struct e1000_hw *hw)
492 hw->mac.ops.init_params = e1000_init_mac_params_82575;
493 hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
494 hw->phy.ops.init_params = e1000_init_phy_params_82575;
495 hw->mbx.ops.init_params = e1000_init_mbx_params_pf;
500 * @hw: pointer to the HW structure
504 static s32 e1000_acquire_phy_82575(struct e1000_hw *hw)
510 if (hw->bus.func == E1000_FUNC_1)
512 else if (hw->bus.func == E1000_FUNC_2)
514 else if (hw->bus.func == E1000_FUNC_3)
517 return hw->mac.ops.acquire_swfw_sync(hw, mask);
522 * @hw: pointer to the HW structure
526 static void e1000_release_phy_82575(struct e1000_hw *hw)
532 if (hw->bus.func == E1000_FUNC_1)
534 else if (hw->bus.func == E1000_FUNC_2)
536 else if (hw->bus.func == E1000_FUNC_3)
539 hw->mac.ops.release_swfw_sync(hw, mask);
544 * @hw: pointer to the HW structure
551 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
563 ret_val = hw->phy.ops.acquire(hw);
567 ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
569 hw->phy.ops.release(hw);
577 * @hw: pointer to the HW structure
584 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
596 ret_val = hw->phy.ops.acquire(hw);
600 ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
602 hw->phy.ops.release(hw);
610 * @hw: pointer to the HW structure
615 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
617 struct e1000_phy_info *phy = &hw->phy;
632 if (!e1000_sgmii_active_82575(hw)) {
634 ret_val = e1000_get_phy_id(hw);
638 if (e1000_sgmii_uses_mdio_82575(hw)) {
639 switch (hw->mac.type) {
642 mdic = E1000_READ_REG(hw, E1000_MDIC);
650 mdic = E1000_READ_REG(hw, E1000_MDICNFG);
659 ret_val = e1000_get_phy_id(hw);
664 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
665 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
667 E1000_WRITE_FLUSH(hw);
675 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
696 ret_val = e1000_get_phy_id(hw);
700 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
708 * @hw: pointer to the HW structure
712 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
725 if (!(hw->phy.ops.write_reg))
732 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
736 ret_val = hw->phy.ops.commit(hw);
744 * @hw: pointer to the HW structure
755 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
757 struct e1000_phy_info *phy = &hw->phy;
763 if (!(hw->phy.ops.read_reg))
766 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
772 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
778 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
781 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
787 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
796 ret_val = phy->ops.read_reg(hw,
803 ret_val = phy->ops.write_reg(hw,
809 ret_val = phy->ops.read_reg(hw,
816 ret_val = phy->ops.write_reg(hw,
830 * @hw: pointer to the HW structure
841 static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
843 struct e1000_phy_info *phy = &hw->phy;
849 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
871 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
877 * @hw: pointer to the HW structure
889 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
891 struct e1000_phy_info *phy = &hw->phy;
897 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
919 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
925 * @hw: pointer to the HW structure
932 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
938 ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
946 if (hw->mac.type == e1000_i350) {
947 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
951 E1000_WRITE_REG(hw, E1000_EECD, eecd |
956 if (hw->mac.type == e1000_82580) {
957 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
960 E1000_WRITE_REG(hw, E1000_EECD, eecd |
967 ret_val = e1000_acquire_nvm_generic(hw);
969 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
977 * @hw: pointer to the HW structure
982 static void e1000_release_nvm_82575(struct e1000_hw *hw)
986 e1000_release_nvm_generic(hw);
988 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
993 * @hw: pointer to the HW structure
999 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1010 if (e1000_get_hw_semaphore_generic(hw)) {
1015 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1023 e1000_put_hw_semaphore_generic(hw);
1035 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1037 e1000_put_hw_semaphore_generic(hw);
1045 * @hw: pointer to the HW structure
1051 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1057 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
1060 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1062 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1064 e1000_put_hw_semaphore_generic(hw);
1069 * @hw: pointer to the HW structure
1077 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
1085 if (hw->bus.func == E1000_FUNC_1)
1087 else if (hw->bus.func == E1000_FUNC_2)
1089 else if (hw->bus.func == E1000_FUNC_3)
1092 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
1101 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
1102 (hw->phy.type == e1000_phy_igp_3))
1103 e1000_phy_init_script_igp3(hw);
1110 * @hw: pointer to the HW structure
1118 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1125 if (hw->phy.media_type != e1000_media_type_copper)
1126 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1129 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1137 * @hw: pointer to the HW structure
1142 static s32 e1000_check_for_link_82575(struct e1000_hw *hw)
1149 if (hw->phy.media_type != e1000_media_type_copper) {
1150 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1157 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1165 ret_val = e1000_config_fc_after_link_up_generic(hw);
1169 ret_val = e1000_check_for_copper_link_generic(hw);
1177 * @hw: pointer to the HW structure
1179 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
1185 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1186 !e1000_sgmii_active_82575(hw))
1190 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1192 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1195 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1197 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1200 E1000_WRITE_FLUSH(hw);
1206 * @hw: pointer to the HW structure
1213 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1216 struct e1000_mac_info *mac = &hw->mac;
1226 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1259 * @hw: pointer to the HW structure
1264 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
1270 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1271 !e1000_sgmii_active_82575(hw))
1274 if (!e1000_enable_mng_pass_thru(hw)) {
1276 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1278 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1281 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1283 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1286 E1000_WRITE_FLUSH(hw);
1295 * @hw: pointer to the HW structure
1299 static s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1310 ret_val = e1000_disable_pcie_master_generic(hw);
1315 ret_val = e1000_set_pcie_completion_timeout(hw);
1320 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1322 E1000_WRITE_REG(hw, E1000_RCTL, 0);
1323 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1324 E1000_WRITE_FLUSH(hw);
1328 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1331 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1333 ret_val = e1000_get_auto_rd_done_generic(hw);
1344 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
1345 e1000_reset_init_script_82575(hw);
1348 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1349 E1000_READ_REG(hw, E1000_ICR);
1352 ret_val = e1000_check_alt_mac_addr_generic(hw);
1359 * @hw: pointer to the HW structure
1363 static s32 e1000_init_hw_82575(struct e1000_hw *hw)
1365 struct e1000_mac_info *mac = &hw->mac;
1372 ret_val = mac->ops.id_led_init(hw);
1380 mac->ops.clear_vfta(hw);
1383 e1000_init_rx_addrs_generic(hw, rar_count);
1388 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1393 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0);
1396 ret_val = mac->ops.setup_link(hw);
1399 hw->dev_spec._82575.mtu = 1500;
1407 e1000_clear_hw_cntrs_82575(hw);
1414 * @hw: pointer to the HW structure
1420 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1428 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1431 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1434 if (hw->mac.type >= e1000_82580) {
1435 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1437 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1440 ret_val = e1000_setup_serdes_link_82575(hw);
1444 if (e1000_sgmii_active_82575(hw)) {
1448 ret_val = hw->phy.ops.reset(hw);
1454 switch (hw->phy.type) {
1457 switch (hw->phy.id) {
1462 ret_val = e1000_copper_link_setup_m88_gen2(hw);
1465 ret_val = e1000_copper_link_setup_m88(hw);
1470 ret_val = e1000_copper_link_setup_igp(hw);
1473 ret_val = e1000_copper_link_setup_82577(hw);
1483 ret_val = e1000_setup_copper_link_generic(hw);
1490 * @hw: pointer to the HW structure
1497 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1506 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1507 !e1000_sgmii_active_82575(hw))
1516 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1519 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1521 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1523 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1527 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)
1530 reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1533 pcs_autoneg = hw->mac.autoneg;
1547 if (hw->mac.type == e1000_82575 ||
1548 hw->mac.type == e1000_82576) {
1549 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1572 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1592 anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1595 switch (hw->fc.requested_mode) {
1608 E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg);
1621 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1623 if (!pcs_autoneg && !e1000_sgmii_active_82575(hw))
1624 e1000_force_mac_fc_generic(hw);
1631 * @hw: pointer to the HW structure
1640 static s32 e1000_get_media_type_82575(struct e1000_hw *hw)
1642 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1652 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1659 hw->phy.media_type = e1000_media_type_internal_serdes;
1662 hw->phy.media_type = e1000_media_type_copper;
1666 if (e1000_sgmii_uses_mdio_82575(hw)) {
1667 hw->phy.media_type = e1000_media_type_copper;
1674 ret_val = e1000_set_sfp_media_type_82575(hw);
1676 (hw->phy.media_type == e1000_media_type_unknown)) {
1681 hw->phy.media_type = e1000_media_type_internal_serdes;
1684 hw->phy.media_type = e1000_media_type_copper;
1698 if (hw->phy.media_type == e1000_media_type_copper)
1703 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1713 * @hw: pointer to the HW structure
1718 static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
1722 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1728 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1730 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
1732 E1000_WRITE_FLUSH(hw);
1736 ret_val = e1000_read_sfp_data_byte(hw,
1747 ret_val = e1000_read_sfp_data_byte(hw,
1758 hw->phy.media_type = e1000_media_type_internal_serdes;
1761 hw->phy.media_type = e1000_media_type_internal_serdes;
1764 hw->phy.media_type = e1000_media_type_copper;
1766 hw->phy.media_type = e1000_media_type_unknown;
1771 hw->phy.media_type = e1000_media_type_unknown;
1776 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1782 * @hw: pointer to the HW structure
1788 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1794 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1801 switch (hw->phy.media_type) {
1817 * @hw: pointer to the HW structure
1823 static bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1825 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1831 * @hw: pointer to the HW structure
1836 static s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
1840 if (hw->mac.type == e1000_82575) {
1843 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1844 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);
1845 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);
1846 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);
1849 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);
1850 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);
1853 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);
1854 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);
1855 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);
1856 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);
1859 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);
1860 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);
1861 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);
1869 * @hw: pointer to the HW structure
1871 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
1882 ret_val = e1000_check_alt_mac_addr_generic(hw);
1886 ret_val = e1000_read_mac_addr_generic(hw);
1894 * @hw: pointer to the HW structure
1899 static void e1000_config_collision_dist_82575(struct e1000_hw *hw)
1905 tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);
1910 E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);
1911 E1000_WRITE_FLUSH(hw);
1916 * @hw: pointer to the HW structure
1921 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw)
1923 struct e1000_phy_info *phy = &hw->phy;
1929 if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw)))
1930 e1000_power_down_phy_copper(hw);
1937 * @hw: pointer to the HW structure
1941 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
1945 e1000_clear_hw_cntrs_base_generic(hw);
1947 E1000_READ_REG(hw, E1000_PRC64);
1948 E1000_READ_REG(hw, E1000_PRC127);
1949 E1000_READ_REG(hw, E1000_PRC255);
1950 E1000_READ_REG(hw, E1000_PRC511);
1951 E1000_READ_REG(hw, E1000_PRC1023);
1952 E1000_READ_REG(hw, E1000_PRC1522);
1953 E1000_READ_REG(hw, E1000_PTC64);
1954 E1000_READ_REG(hw, E1000_PTC127);
1955 E1000_READ_REG(hw, E1000_PTC255);
1956 E1000_READ_REG(hw, E1000_PTC511);
1957 E1000_READ_REG(hw, E1000_PTC1023);
1958 E1000_READ_REG(hw, E1000_PTC1522);
1960 E1000_READ_REG(hw, E1000_ALGNERRC);
1961 E1000_READ_REG(hw, E1000_RXERRC);
1962 E1000_READ_REG(hw, E1000_TNCRS);
1963 E1000_READ_REG(hw, E1000_CEXTERR);
1964 E1000_READ_REG(hw, E1000_TSCTC);
1965 E1000_READ_REG(hw, E1000_TSCTFC);
1967 E1000_READ_REG(hw, E1000_MGTPRC);
1968 E1000_READ_REG(hw, E1000_MGTPDC);
1969 E1000_READ_REG(hw, E1000_MGTPTC);
1971 E1000_READ_REG(hw, E1000_IAC);
1972 E1000_READ_REG(hw, E1000_ICRXOC);
1974 E1000_READ_REG(hw, E1000_ICRXPTC);
1975 E1000_READ_REG(hw, E1000_ICRXATC);
1976 E1000_READ_REG(hw, E1000_ICTXPTC);
1977 E1000_READ_REG(hw, E1000_ICTXATC);
1978 E1000_READ_REG(hw, E1000_ICTXQEC);
1979 E1000_READ_REG(hw, E1000_ICTXQMTC);
1980 E1000_READ_REG(hw, E1000_ICRXDMTC);
1982 E1000_READ_REG(hw, E1000_CBTMPC);
1983 E1000_READ_REG(hw, E1000_HTDPMC);
1984 E1000_READ_REG(hw, E1000_CBRMPC);
1985 E1000_READ_REG(hw, E1000_RPTHC);
1986 E1000_READ_REG(hw, E1000_HGPTC);
1987 E1000_READ_REG(hw, E1000_HTCBDPC);
1988 E1000_READ_REG(hw, E1000_HGORCL);
1989 E1000_READ_REG(hw, E1000_HGORCH);
1990 E1000_READ_REG(hw, E1000_HGOTCL);
1991 E1000_READ_REG(hw, E1000_HGOTCH);
1992 E1000_READ_REG(hw, E1000_LENERRS);
1995 if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
1996 e1000_sgmii_active_82575(hw))
1997 E1000_READ_REG(hw, E1000_SCVPC);
2002 * @hw: pointer to the HW structure
2009 void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
2015 if (hw->mac.type != e1000_82575 ||
2016 !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
2021 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
2022 E1000_WRITE_REG(hw, E1000_RXDCTL(i),
2030 rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));
2042 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2043 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
2045 rlpml = E1000_READ_REG(hw, E1000_RLPML);
2046 E1000_WRITE_REG(hw, E1000_RLPML, 0);
2048 rctl = E1000_READ_REG(hw, E1000_RCTL);
2052 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);
2053 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);
2054 E1000_WRITE_FLUSH(hw);
2061 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);
2062 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2063 E1000_WRITE_FLUSH(hw);
2065 E1000_WRITE_REG(hw, E1000_RLPML, rlpml);
2066 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2069 E1000_READ_REG(hw, E1000_ROC);
2070 E1000_READ_REG(hw, E1000_RNBC);
2071 E1000_READ_REG(hw, E1000_MPC);
2076 * @hw: pointer to the HW structure
2084 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
2086 u32 gcr = E1000_READ_REG(hw, E1000_GCR);
2108 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2115 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2121 E1000_WRITE_REG(hw, E1000_GCR, gcr);
2127 * @hw: pointer to the hardware struct
2133 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2137 switch (hw->mac.type) {
2139 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2151 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2154 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2167 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2175 * @hw: pointer to the hardware struct
2180 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2184 switch (hw->mac.type) {
2186 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2191 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2194 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2199 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2211 * @hw: pointer to the hardware struct
2216 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2218 u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
2225 E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
2230 * @hw: pointer to the HW structure
2237 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2243 ret_val = hw->phy.ops.acquire(hw);
2247 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
2249 hw->phy.ops.release(hw);
2257 * @hw: pointer to the HW structure
2263 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2269 ret_val = hw->phy.ops.acquire(hw);
2273 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2275 hw->phy.ops.release(hw);
2283 * @hw: pointer to the HW structure
2289 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
2297 if (hw->mac.type != e1000_82580)
2299 if (!e1000_sgmii_active_82575(hw))
2302 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2303 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2310 mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
2315 E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
2322 * @hw: pointer to the HW structure
2327 static s32 e1000_reset_hw_82580(struct e1000_hw *hw)
2333 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2337 hw->dev_spec._82575.global_device_reset = FALSE;
2339 /* 82580 does not reliably do global_device_reset due to hw errata */
2340 if (hw->mac.type == e1000_82580)
2344 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2350 ret_val = e1000_disable_pcie_master_generic(hw);
2355 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2356 E1000_WRITE_REG(hw, E1000_RCTL, 0);
2357 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2358 E1000_WRITE_FLUSH(hw);
2363 if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,
2367 if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
2373 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2374 E1000_WRITE_FLUSH(hw);
2380 ret_val = e1000_get_auto_rd_done_generic(hw);
2391 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
2392 e1000_reset_init_script_82575(hw);
2395 E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
2398 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2399 E1000_READ_REG(hw, E1000_ICR);
2401 ret_val = e1000_reset_mdicnfg_82580(hw);
2406 ret_val = e1000_check_alt_mac_addr_generic(hw);
2410 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2438 * @hw: pointer to the HW structure
2444 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2453 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2474 * @hw: pointer to the HW structure
2481 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2490 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2498 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2509 * @hw: pointer to the HW structure
2515 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
2524 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2538 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2550 * @hw: pointer to the HW structure
2556 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
2564 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2573 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2583 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2594 * @hw: pointer to the HW structure
2600 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
2610 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2622 * @hw: pointer to the HW structure
2628 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
2638 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2649 * @hw: pointer to the HW structure
2654 s32 e1000_set_eee_i350(struct e1000_hw *hw)
2661 if ((hw->mac.type < e1000_i350) ||
2662 (hw->phy.media_type != e1000_media_type_copper))
2664 ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
2665 eeer = E1000_READ_REG(hw, E1000_EEER);
2668 if (!(hw->dev_spec._82575.eee_disable)) {
2669 u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);
2683 E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
2684 E1000_WRITE_REG(hw, E1000_EEER, eeer);
2685 E1000_READ_REG(hw, E1000_IPCNFG);
2686 E1000_READ_REG(hw, E1000_EEER);
2692 /* Due to a hw errata, if the host tries to configure the VFTA register
2699 * @hw: pointer to the HW structure
2704 void e1000_clear_vfta_i350(struct e1000_hw *hw)
2713 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
2715 E1000_WRITE_FLUSH(hw);
2721 * @hw: pointer to the HW structure
2728 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
2735 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
2737 E1000_WRITE_FLUSH(hw);
2743 * @hw: pointer to the HW structure
2748 s32 e1000_set_i2c_bb(struct e1000_hw *hw)
2755 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2757 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2758 E1000_WRITE_FLUSH(hw);
2760 i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);
2764 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);
2765 E1000_WRITE_FLUSH(hw);
2772 * @hw: pointer to hardware structure
2780 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
2795 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
2801 e1000_i2c_start(hw);
2804 status = e1000_clock_out_i2c_byte(hw, dev_addr);
2808 status = e1000_get_i2c_ack(hw);
2812 status = e1000_clock_out_i2c_byte(hw, byte_offset);
2816 status = e1000_get_i2c_ack(hw);
2820 e1000_i2c_start(hw);
2823 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2827 status = e1000_get_i2c_ack(hw);
2831 status = e1000_clock_in_i2c_byte(hw, data);
2835 status = e1000_clock_out_i2c_bit(hw, nack);
2839 e1000_i2c_stop(hw);
2843 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2845 e1000_i2c_bus_clear(hw);
2854 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2863 * @hw: pointer to hardware structure
2871 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
2883 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) {
2889 e1000_i2c_start(hw);
2891 status = e1000_clock_out_i2c_byte(hw, dev_addr);
2895 status = e1000_get_i2c_ack(hw);
2899 status = e1000_clock_out_i2c_byte(hw, byte_offset);
2903 status = e1000_get_i2c_ack(hw);
2907 status = e1000_clock_out_i2c_byte(hw, data);
2911 status = e1000_get_i2c_ack(hw);
2915 e1000_i2c_stop(hw);
2919 e1000_i2c_bus_clear(hw);
2927 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2936 * @hw: pointer to hardware structure
2940 static void e1000_i2c_start(struct e1000_hw *hw)
2942 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
2947 e1000_set_i2c_data(hw, &i2cctl, 1);
2948 e1000_raise_i2c_clk(hw, &i2cctl);
2953 e1000_set_i2c_data(hw, &i2cctl, 0);
2958 e1000_lower_i2c_clk(hw, &i2cctl);
2967 * @hw: pointer to hardware structure
2971 static void e1000_i2c_stop(struct e1000_hw *hw)
2973 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
2978 e1000_set_i2c_data(hw, &i2cctl, 0);
2979 e1000_raise_i2c_clk(hw, &i2cctl);
2984 e1000_set_i2c_data(hw, &i2cctl, 1);
2992 * @hw: pointer to hardware structure
2997 static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)
3006 e1000_clock_in_i2c_bit(hw, &bit);
3015 * @hw: pointer to hardware structure
3020 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)
3031 status = e1000_clock_out_i2c_bit(hw, bit);
3038 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3041 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);
3042 E1000_WRITE_FLUSH(hw);
3049 * @hw: pointer to hardware structure
3053 static s32 e1000_get_i2c_ack(struct e1000_hw *hw)
3057 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3063 e1000_raise_i2c_clk(hw, &i2cctl);
3071 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3084 e1000_lower_i2c_clk(hw, &i2cctl);
3094 * @hw: pointer to hardware structure
3099 static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)
3101 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3105 e1000_raise_i2c_clk(hw, &i2cctl);
3110 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3113 e1000_lower_i2c_clk(hw, &i2cctl);
3123 * @hw: pointer to hardware structure
3128 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)
3131 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3135 status = e1000_set_i2c_data(hw, &i2cctl, data);
3137 e1000_raise_i2c_clk(hw, &i2cctl);
3142 e1000_lower_i2c_clk(hw, &i2cctl);
3157 * @hw: pointer to hardware structure
3162 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3168 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3169 E1000_WRITE_FLUSH(hw);
3177 * @hw: pointer to hardware structure
3182 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3189 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3190 E1000_WRITE_FLUSH(hw);
3198 * @hw: pointer to hardware structure
3204 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)
3217 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3218 E1000_WRITE_FLUSH(hw);
3223 *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3234 * @hw: pointer to hardware structure
3255 * @hw: pointer to hardware structure
3260 void e1000_i2c_bus_clear(struct e1000_hw *hw)
3262 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3267 e1000_i2c_start(hw);
3269 e1000_set_i2c_data(hw, &i2cctl, 1);
3272 e1000_raise_i2c_clk(hw, &i2cctl);
3277 e1000_lower_i2c_clk(hw, &i2cctl);
3283 e1000_i2c_start(hw);
3286 e1000_i2c_stop(hw);