Lines Matching refs:hw
53 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw);
54 static void e1000_release_nvm_82571(struct e1000_hw *hw);
55 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset,
57 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw);
58 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw);
59 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw);
60 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw,
62 static s32 e1000_reset_hw_82571(struct e1000_hw *hw);
63 static s32 e1000_init_hw_82571(struct e1000_hw *hw);
64 static void e1000_clear_vfta_82571(struct e1000_hw *hw);
65 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
66 static s32 e1000_led_on_82574(struct e1000_hw *hw);
67 static s32 e1000_setup_link_82571(struct e1000_hw *hw);
68 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
69 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
70 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
71 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data);
72 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
73 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw);
74 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
75 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
76 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
77 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
78 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
79 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
80 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw,
82 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw,
84 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
85 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
87 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw);
88 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
92 * @hw: pointer to the HW structure
94 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
96 struct e1000_phy_info *phy = &hw->phy;
101 if (hw->phy.media_type != e1000_media_type_copper) {
117 switch (hw->mac.type) {
146 E1000_MUTEX_INIT(&hw->dev_spec._82571.swflag_mutex);
168 ret_val = e1000_get_phy_id_82571(hw);
175 switch (hw->mac.type) {
203 * @hw: pointer to the HW structure
205 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
207 struct e1000_nvm_info *nvm = &hw->nvm;
208 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
230 switch (hw->mac.type) {
241 E1000_WRITE_REG(hw, E1000_EECD, eecd);
262 switch (hw->mac.type) {
284 * @hw: pointer to the HW structure
286 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
288 struct e1000_mac_info *mac = &hw->mac;
296 switch (hw->device_id) {
300 hw->phy.media_type = e1000_media_type_fiber;
311 hw->phy.media_type = e1000_media_type_internal_serdes;
319 hw->phy.media_type = e1000_media_type_copper;
343 /* hw initialization */
367 switch (hw->mac.type) {
379 mac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) &
404 switch (hw->mac.type) {
407 swsm2 = E1000_READ_REG(hw, E1000_SWSM2);
411 E1000_WRITE_REG(hw, E1000_SWSM2, swsm2 |
425 swsm = E1000_READ_REG(hw, E1000_SWSM);
433 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_SMBI);
437 hw->dev_spec._82571.smb_counter = 0;
444 * @hw: pointer to the HW structure
448 void e1000_init_function_pointers_82571(struct e1000_hw *hw)
452 hw->mac.ops.init_params = e1000_init_mac_params_82571;
453 hw->nvm.ops.init_params = e1000_init_nvm_params_82571;
454 hw->phy.ops.init_params = e1000_init_phy_params_82571;
459 * @hw: pointer to the HW structure
464 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
466 struct e1000_phy_info *phy = &hw->phy;
472 switch (hw->mac.type) {
483 return e1000_get_phy_id(hw);
487 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
493 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
510 * @hw: pointer to the HW structure
514 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
517 s32 sw_timeout = hw->nvm.word_size + 1;
518 s32 fw_timeout = hw->nvm.word_size + 1;
530 if (hw->dev_spec._82571.smb_counter > 2)
535 swsm = E1000_READ_REG(hw, E1000_SWSM);
545 hw->dev_spec._82571.smb_counter++;
549 swsm = E1000_READ_REG(hw, E1000_SWSM);
550 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
553 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
561 e1000_put_hw_semaphore_82571(hw);
571 * @hw: pointer to the HW structure
575 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
581 swsm = E1000_READ_REG(hw, E1000_SWSM);
585 E1000_WRITE_REG(hw, E1000_SWSM, swsm);
590 * @hw: pointer to the HW structure
595 static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)
602 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
605 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
606 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
617 e1000_put_hw_semaphore_82573(hw);
627 * @hw: pointer to the HW structure
632 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)
638 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
640 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
645 * @hw: pointer to the HW structure
650 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
656 E1000_MUTEX_LOCK(&hw->dev_spec._82571.swflag_mutex);
657 ret_val = e1000_get_hw_semaphore_82573(hw);
659 E1000_MUTEX_UNLOCK(&hw->dev_spec._82571.swflag_mutex);
665 * @hw: pointer to the HW structure
670 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
674 e1000_put_hw_semaphore_82573(hw);
675 E1000_MUTEX_UNLOCK(&hw->dev_spec._82571.swflag_mutex);
680 * @hw: pointer to the HW structure
690 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active)
692 u32 data = E1000_READ_REG(hw, E1000_POEMB);
701 E1000_WRITE_REG(hw, E1000_POEMB, data);
707 * @hw: pointer to the HW structure
716 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active)
718 u32 data = E1000_READ_REG(hw, E1000_POEMB);
724 } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
725 (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||
726 (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {
730 E1000_WRITE_REG(hw, E1000_POEMB, data);
736 * @hw: pointer to the HW structure
743 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
749 ret_val = e1000_get_hw_semaphore_82571(hw);
753 switch (hw->mac.type) {
757 ret_val = e1000_acquire_nvm_generic(hw);
762 e1000_put_hw_semaphore_82571(hw);
769 * @hw: pointer to the HW structure
773 static void e1000_release_nvm_82571(struct e1000_hw *hw)
777 e1000_release_nvm_generic(hw);
778 e1000_put_hw_semaphore_82571(hw);
783 * @hw: pointer to the HW structure
793 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
800 switch (hw->mac.type) {
804 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
808 ret_val = e1000_write_nvm_spi(hw, offset, words, data);
820 * @hw: pointer to the HW structure
826 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
834 ret_val = e1000_update_nvm_checksum_generic(hw);
841 if (hw->nvm.type != e1000_nvm_flash_hw)
847 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD))
855 if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) {
859 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE);
860 E1000_WRITE_FLUSH(hw);
861 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET);
865 eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD;
866 E1000_WRITE_REG(hw, E1000_EECD, eecd);
870 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD))
882 * @hw: pointer to the HW structure
887 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
891 if (hw->nvm.type == e1000_nvm_flash_hw)
892 e1000_fix_nvm_checksum_82571(hw);
894 return e1000_validate_nvm_checksum_generic(hw);
899 * @hw: pointer to the HW structure
911 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
914 struct e1000_nvm_info *nvm = &hw->nvm;
934 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
938 E1000_WRITE_REG(hw, E1000_EEWR, eewr);
940 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
950 * @hw: pointer to the HW structure
954 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
961 if (E1000_READ_REG(hw, E1000_EEMNGCTL) &
977 * @hw: pointer to the HW structure
986 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
988 struct e1000_phy_info *phy = &hw->phy;
997 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1003 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1009 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1014 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1020 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1028 ret_val = phy->ops.read_reg(hw,
1035 ret_val = phy->ops.write_reg(hw,
1041 ret_val = phy->ops.read_reg(hw,
1048 ret_val = phy->ops.write_reg(hw,
1061 * @hw: pointer to the HW structure
1065 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
1075 ret_val = e1000_disable_pcie_master_generic(hw);
1080 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1082 E1000_WRITE_REG(hw, E1000_RCTL, 0);
1083 tctl = E1000_READ_REG(hw, E1000_TCTL);
1085 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1086 E1000_WRITE_FLUSH(hw);
1093 switch (hw->mac.type) {
1095 ret_val = e1000_get_hw_semaphore_82573(hw);
1099 ret_val = e1000_get_hw_semaphore_82574(hw);
1107 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1110 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1113 switch (hw->mac.type) {
1116 e1000_put_hw_semaphore_82574(hw);
1122 if (hw->nvm.type == e1000_nvm_flash_hw) {
1124 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1126 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1127 E1000_WRITE_FLUSH(hw);
1130 ret_val = e1000_get_auto_rd_done_generic(hw);
1140 switch (hw->mac.type) {
1146 eecd = E1000_READ_REG(hw, E1000_EECD);
1148 E1000_WRITE_REG(hw, E1000_EECD, eecd);
1160 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1161 E1000_READ_REG(hw, E1000_ICR);
1163 if (hw->mac.type == e1000_82571) {
1165 ret_val = e1000_check_alt_mac_addr_generic(hw);
1169 e1000_set_laa_state_82571(hw, TRUE);
1173 if (hw->phy.media_type == e1000_media_type_internal_serdes)
1174 hw->mac.serdes_link_state = e1000_serdes_link_down;
1181 * @hw: pointer to the HW structure
1185 static s32 e1000_init_hw_82571(struct e1000_hw *hw)
1187 struct e1000_mac_info *mac = &hw->mac;
1194 e1000_initialize_hw_bits_82571(hw);
1197 ret_val = mac->ops.id_led_init(hw);
1204 mac->ops.clear_vfta(hw);
1211 if (e1000_get_laa_state_82571(hw))
1213 e1000_init_rx_addrs_generic(hw, rar_count);
1218 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1221 ret_val = mac->ops.setup_link(hw);
1224 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
1227 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
1232 e1000_enable_tx_pkt_filtering_generic(hw);
1236 reg_data = E1000_READ_REG(hw, E1000_GCR);
1238 E1000_WRITE_REG(hw, E1000_GCR, reg_data);
1241 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
1245 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
1254 e1000_clear_hw_cntrs_82571(hw);
1261 * @hw: pointer to the HW structure
1265 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1272 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
1274 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
1277 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
1279 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
1282 reg = E1000_READ_REG(hw, E1000_TARC(0));
1284 switch (hw->mac.type) {
1296 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
1299 reg = E1000_READ_REG(hw, E1000_TARC(1));
1300 switch (hw->mac.type) {
1305 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
1309 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
1316 switch (hw->mac.type) {
1320 reg = E1000_READ_REG(hw, E1000_CTRL);
1322 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1329 switch (hw->mac.type) {
1333 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1336 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1342 if (hw->mac.type == e1000_82571) {
1343 reg = E1000_READ_REG(hw, E1000_PBA_ECC);
1345 E1000_WRITE_REG(hw, E1000_PBA_ECC, reg);
1351 if ((hw->mac.type == e1000_82571) ||
1352 (hw->mac.type == e1000_82572)) {
1353 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1355 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1361 if (hw->mac.type <= e1000_82573) {
1362 reg = E1000_READ_REG(hw, E1000_RFCTL);
1364 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
1368 switch (hw->mac.type) {
1371 reg = E1000_READ_REG(hw, E1000_GCR);
1373 E1000_WRITE_REG(hw, E1000_GCR, reg);
1381 reg = E1000_READ_REG(hw, E1000_GCR2);
1383 E1000_WRITE_REG(hw, E1000_GCR2, reg);
1394 * @hw: pointer to the HW structure
1399 static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1408 switch (hw->mac.type) {
1412 if (hw->mng_cookie.vlan_id != 0) {
1419 vfta_offset = (hw->mng_cookie.vlan_id >>
1423 1 << (hw->mng_cookie.vlan_id &
1436 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1437 E1000_WRITE_FLUSH(hw);
1443 * @hw: pointer to the HW structure
1448 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1454 hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1460 * @hw: pointer to the HW structure
1464 static s32 e1000_led_on_82574(struct e1000_hw *hw)
1471 ctrl = hw->mac.ledctl_mode2;
1472 if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) {
1477 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1481 E1000_WRITE_REG(hw, E1000_LEDCTL, ctrl);
1488 * @hw: pointer to the HW structure
1492 bool e1000_check_phy_82574(struct e1000_hw *hw)
1503 ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER,
1508 ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS,
1523 * @hw: pointer to the HW structure
1531 static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1539 switch (hw->mac.type) {
1543 if (hw->fc.requested_mode == e1000_fc_default)
1544 hw->fc.requested_mode = e1000_fc_full;
1550 return e1000_setup_link_generic(hw);
1555 * @hw: pointer to the HW structure
1561 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1568 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1571 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1573 switch (hw->phy.type) {
1576 ret_val = e1000_copper_link_setup_m88(hw);
1579 ret_val = e1000_copper_link_setup_igp(hw);
1589 return e1000_setup_copper_link_generic(hw);
1594 * @hw: pointer to the HW structure
1599 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1603 switch (hw->mac.type) {
1612 E1000_WRITE_REG(hw, E1000_SCTL,
1619 return e1000_setup_fiber_serdes_link_generic(hw);
1624 * @hw: pointer to the HW structure
1641 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1643 struct e1000_mac_info *mac = &hw->mac;
1653 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1654 status = E1000_READ_REG(hw, E1000_STATUS);
1655 E1000_READ_REG(hw, E1000_RXCW);
1658 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1685 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1686 E1000_WRITE_REG(hw, E1000_CTRL,
1719 E1000_WRITE_REG(hw, E1000_TXCW,
1722 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1726 e1000_config_fc_after_link_up_generic(hw);
1744 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1745 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl &
1765 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1780 txcw = E1000_READ_REG(hw, E1000_TXCW);
1782 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1796 * @hw: pointer to the HW structure
1802 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1808 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1814 switch (hw->mac.type) {
1833 * @hw: pointer to the HW structure
1837 bool e1000_get_laa_state_82571(struct e1000_hw *hw)
1841 if (hw->mac.type != e1000_82571)
1844 return hw->dev_spec._82571.laa_is_present;
1849 * @hw: pointer to the HW structure
1854 void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state)
1858 if (hw->mac.type != e1000_82571)
1861 hw->dev_spec._82571.laa_is_present = state;
1871 hw->mac.ops.rar_set(hw, hw->mac.addr,
1872 hw->mac.rar_entry_count - 1);
1878 * @hw: pointer to the HW structure
1886 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1888 struct e1000_nvm_info *nvm = &hw->nvm;
1900 ret_val = nvm->ops.read(hw, 0x10, 1, &data);
1912 ret_val = nvm->ops.read(hw, 0x23, 1, &data);
1918 ret_val = nvm->ops.write(hw, 0x23, 1, &data);
1921 ret_val = nvm->ops.update(hw);
1933 * @hw: pointer to the HW structure
1935 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1939 if (hw->mac.type == e1000_82571) {
1946 ret_val = e1000_check_alt_mac_addr_generic(hw);
1951 return e1000_read_mac_addr_generic(hw);
1956 * @hw: pointer to the HW structure
1961 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1963 struct e1000_phy_info *phy = &hw->phy;
1964 struct e1000_mac_info *mac = &hw->mac;
1970 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1971 e1000_power_down_phy_copper(hw);
1978 * @hw: pointer to the HW structure
1982 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1986 e1000_clear_hw_cntrs_base_generic(hw);
1988 E1000_READ_REG(hw, E1000_PRC64);
1989 E1000_READ_REG(hw, E1000_PRC127);
1990 E1000_READ_REG(hw, E1000_PRC255);
1991 E1000_READ_REG(hw, E1000_PRC511);
1992 E1000_READ_REG(hw, E1000_PRC1023);
1993 E1000_READ_REG(hw, E1000_PRC1522);
1994 E1000_READ_REG(hw, E1000_PTC64);
1995 E1000_READ_REG(hw, E1000_PTC127);
1996 E1000_READ_REG(hw, E1000_PTC255);
1997 E1000_READ_REG(hw, E1000_PTC511);
1998 E1000_READ_REG(hw, E1000_PTC1023);
1999 E1000_READ_REG(hw, E1000_PTC1522);
2001 E1000_READ_REG(hw, E1000_ALGNERRC);
2002 E1000_READ_REG(hw, E1000_RXERRC);
2003 E1000_READ_REG(hw, E1000_TNCRS);
2004 E1000_READ_REG(hw, E1000_CEXTERR);
2005 E1000_READ_REG(hw, E1000_TSCTC);
2006 E1000_READ_REG(hw, E1000_TSCTFC);
2008 E1000_READ_REG(hw, E1000_MGTPRC);
2009 E1000_READ_REG(hw, E1000_MGTPDC);
2010 E1000_READ_REG(hw, E1000_MGTPTC);
2012 E1000_READ_REG(hw, E1000_IAC);
2013 E1000_READ_REG(hw, E1000_ICRXOC);
2015 E1000_READ_REG(hw, E1000_ICRXPTC);
2016 E1000_READ_REG(hw, E1000_ICRXATC);
2017 E1000_READ_REG(hw, E1000_ICTXPTC);
2018 E1000_READ_REG(hw, E1000_ICTXATC);
2019 E1000_READ_REG(hw, E1000_ICTXQEC);
2020 E1000_READ_REG(hw, E1000_ICTXQMTC);
2021 E1000_READ_REG(hw, E1000_ICRXDMTC);