Lines Matching refs:hw
46 static s32 e1000_init_phy_params_82543(struct e1000_hw *hw);
47 static s32 e1000_init_nvm_params_82543(struct e1000_hw *hw);
48 static s32 e1000_init_mac_params_82543(struct e1000_hw *hw);
49 static s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset,
51 static s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset,
53 static s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw);
54 static s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw);
55 static s32 e1000_reset_hw_82543(struct e1000_hw *hw);
56 static s32 e1000_init_hw_82543(struct e1000_hw *hw);
57 static s32 e1000_setup_link_82543(struct e1000_hw *hw);
58 static s32 e1000_setup_copper_link_82543(struct e1000_hw *hw);
59 static s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw);
60 static s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw);
61 static s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw);
62 static s32 e1000_led_on_82543(struct e1000_hw *hw);
63 static s32 e1000_led_off_82543(struct e1000_hw *hw);
64 static void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset,
66 static void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw);
67 static s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw);
68 static bool e1000_init_phy_disabled_82543(struct e1000_hw *hw);
69 static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl);
70 static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw);
71 static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl);
72 static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw);
73 static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data,
75 static bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw);
76 static void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state);
77 static s32 e1000_read_mac_addr_82543(struct e1000_hw *hw);
82 * @hw: pointer to the HW structure
84 static s32 e1000_init_phy_params_82543(struct e1000_hw *hw)
86 struct e1000_phy_info *phy = &hw->phy;
91 if (hw->phy.media_type != e1000_media_type_copper) {
110 phy->ops.read_reg = (hw->mac.type == e1000_82543)
113 phy->ops.reset = (hw->mac.type == e1000_82543)
116 phy->ops.write_reg = (hw->mac.type == e1000_82543)
126 if (!e1000_init_phy_disabled_82543(hw)) {
127 ret_val = phy->ops.reset(hw);
135 ret_val = e1000_get_phy_id(hw);
140 switch (hw->mac.type) {
165 * @hw: pointer to the HW structure
167 static s32 e1000_init_nvm_params_82543(struct e1000_hw *hw)
169 struct e1000_nvm_info *nvm = &hw->nvm;
191 * @hw: pointer to the HW structure
193 static s32 e1000_init_mac_params_82543(struct e1000_hw *hw)
195 struct e1000_mac_info *mac = &hw->mac;
200 switch (hw->device_id) {
203 hw->phy.media_type = e1000_media_type_fiber;
206 hw->phy.media_type = e1000_media_type_copper;
223 /* hw initialization */
229 (hw->phy.media_type == e1000_media_type_copper)
234 (hw->phy.media_type == e1000_media_type_copper)
239 (hw->phy.media_type == e1000_media_type_copper)
257 if ((hw->mac.type != e1000_82543) ||
258 (hw->phy.media_type == e1000_media_type_fiber))
259 e1000_set_tbi_compatibility_82543(hw, FALSE);
266 * @hw: pointer to the HW structure
270 void e1000_init_function_pointers_82543(struct e1000_hw *hw)
274 hw->mac.ops.init_params = e1000_init_mac_params_82543;
275 hw->nvm.ops.init_params = e1000_init_nvm_params_82543;
276 hw->phy.ops.init_params = e1000_init_phy_params_82543;
281 * @hw: pointer to the HW structure
286 static bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw)
288 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
293 if (hw->mac.type != e1000_82543) {
307 * @hw: pointer to the HW structure
312 void e1000_set_tbi_compatibility_82543(struct e1000_hw *hw, bool state)
314 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
318 if (hw->mac.type != e1000_82543) {
334 * @hw: pointer to the HW structure
339 bool e1000_tbi_sbp_enabled_82543(struct e1000_hw *hw)
341 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
346 if (hw->mac.type != e1000_82543) {
360 * @hw: pointer to the HW structure
365 static void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state)
367 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
371 if (state && e1000_tbi_compatibility_enabled_82543(hw))
381 * @hw: pointer to the HW structure
386 static bool e1000_init_phy_disabled_82543(struct e1000_hw *hw)
388 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
393 if (hw->mac.type != e1000_82543) {
406 * @hw: pointer to the HW structure
414 void e1000_tbi_adjust_stats_82543(struct e1000_hw *hw,
418 if (!(e1000_tbi_sbp_enabled_82543(hw)))
484 * @hw: pointer to the HW structure
490 static s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 *data)
508 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
522 mdic = (offset | (hw->phy.addr << 5) |
525 e1000_shift_out_mdi_bits_82543(hw, mdic, 14);
532 *data = e1000_shift_in_mdi_bits_82543(hw);
540 * @hw: pointer to the HW structure
546 static s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 data)
565 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
574 mdic = ((PHY_TURNAROUND) | (offset << 2) | (hw->phy.addr << 7) |
579 e1000_shift_out_mdi_bits_82543(hw, mdic, 32);
587 * @hw: pointer to the HW structure
593 static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl)
599 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl | E1000_CTRL_MDC));
600 E1000_WRITE_FLUSH(hw);
606 * @hw: pointer to the HW structure
612 static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl)
618 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl & ~E1000_CTRL_MDC));
619 E1000_WRITE_FLUSH(hw);
625 * @hw: pointer to the HW structure
633 static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data,
647 ctrl = E1000_READ_REG(hw, E1000_CTRL);
662 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
663 E1000_WRITE_FLUSH(hw);
667 e1000_raise_mdi_clk_82543(hw, &ctrl);
668 e1000_lower_mdi_clk_82543(hw, &ctrl);
676 * @hw: pointer to the HW structure
683 static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw)
698 ctrl = E1000_READ_REG(hw, E1000_CTRL);
707 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
708 E1000_WRITE_FLUSH(hw);
715 e1000_raise_mdi_clk_82543(hw, &ctrl);
716 e1000_lower_mdi_clk_82543(hw, &ctrl);
720 e1000_raise_mdi_clk_82543(hw, &ctrl);
721 ctrl = E1000_READ_REG(hw, E1000_CTRL);
725 e1000_lower_mdi_clk_82543(hw, &ctrl);
728 e1000_raise_mdi_clk_82543(hw, &ctrl);
729 e1000_lower_mdi_clk_82543(hw, &ctrl);
736 * @hw: pointer to the HW structure
742 static s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw)
748 ret_val = e1000_phy_force_speed_duplex_m88(hw);
752 if (!hw->mac.autoneg &&
753 (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED))
754 ret_val = e1000_polarity_reversal_workaround_82543(hw);
762 * @hw: pointer to the HW structure
768 static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw)
775 if (!(hw->phy.ops.write_reg))
782 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
785 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
789 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
803 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
807 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
821 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
825 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
829 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
833 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
837 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
845 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_TIME, 100000, &link);
855 * @hw: pointer to the HW structure
862 static s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw)
873 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
876 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
877 E1000_WRITE_FLUSH(hw);
883 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
884 E1000_WRITE_FLUSH(hw);
888 if (!(hw->phy.ops.get_cfg_done))
891 ret_val = hw->phy.ops.get_cfg_done(hw);
898 * @hw: pointer to the HW structure
902 static s32 e1000_reset_hw_82543(struct e1000_hw *hw)
910 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
912 E1000_WRITE_REG(hw, E1000_RCTL, 0);
913 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
914 E1000_WRITE_FLUSH(hw);
916 e1000_set_tbi_sbp_82543(hw, FALSE);
924 ctrl = E1000_READ_REG(hw, E1000_CTRL);
927 if (hw->mac.type == e1000_82543) {
928 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
934 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
941 hw->nvm.ops.reload(hw);
945 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
946 icr = E1000_READ_REG(hw, E1000_ICR);
953 * @hw: pointer to the HW structure
957 static s32 e1000_init_hw_82543(struct e1000_hw *hw)
959 struct e1000_mac_info *mac = &hw->mac;
960 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
968 E1000_WRITE_REG(hw, E1000_VET, 0);
969 mac->ops.clear_vfta(hw);
972 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
977 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
978 E1000_WRITE_FLUSH(hw);
986 if (hw->mac.type == e1000_82543 && dev_spec->dma_fairness) {
987 ctrl = E1000_READ_REG(hw, E1000_CTRL);
988 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR);
991 e1000_pcix_mmrbc_workaround_generic(hw);
994 ret_val = mac->ops.setup_link(hw);
1002 e1000_clear_hw_cntrs_82543(hw);
1009 * @hw: pointer to the HW structure
1020 static s32 e1000_setup_link_82543(struct e1000_hw *hw)
1035 if (hw->mac.type == e1000_82543) {
1036 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1044 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1047 ret_val = e1000_setup_link_generic(hw);
1055 * @hw: pointer to the HW structure
1061 static s32 e1000_setup_copper_link_82543(struct e1000_hw *hw)
1069 ctrl = E1000_READ_REG(hw, E1000_CTRL) | E1000_CTRL_SLU;
1076 if (hw->mac.type == e1000_82543) {
1078 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1079 ret_val = hw->phy.ops.reset(hw);
1084 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1088 ret_val = e1000_copper_link_setup_m88(hw);
1092 if (hw->mac.autoneg) {
1097 ret_val = e1000_copper_link_autoneg(hw);
1106 ret_val = e1000_phy_force_speed_duplex_82543(hw);
1117 ret_val = e1000_phy_has_link_generic(hw,
1128 if (hw->mac.type == e1000_82544) {
1129 hw->mac.ops.config_collision_dist(hw);
1131 ret_val = e1000_config_mac_to_phy_82543(hw);
1135 ret_val = e1000_config_fc_after_link_up_generic(hw);
1146 * @hw: pointer to the HW structure
1151 static s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw)
1158 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1163 hw->mac.ops.config_collision_dist(hw);
1165 ret_val = e1000_commit_fc_settings_generic(hw);
1171 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1172 E1000_WRITE_FLUSH(hw);
1180 if (!(E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {
1181 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
1192 * @hw: pointer to the HW structure
1201 static s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw)
1203 struct e1000_mac_info *mac = &hw->mac;
1216 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1225 e1000_check_downshift_generic(hw);
1241 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
1242 ret_val = e1000_polarity_reversal_workaround_82543(hw);
1243 icr = E1000_READ_REG(hw, E1000_ICR);
1244 E1000_WRITE_REG(hw, E1000_ICS, (icr & ~E1000_ICS_LSC));
1245 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK);
1262 hw->mac.ops.config_collision_dist(hw);
1264 ret_val = e1000_config_mac_to_phy_82543(hw);
1277 ret_val = e1000_config_fc_after_link_up_generic(hw);
1290 if (e1000_tbi_compatibility_enabled_82543(hw)) {
1291 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1301 if (e1000_tbi_sbp_enabled_82543(hw)) {
1306 e1000_set_tbi_sbp_82543(hw, FALSE);
1307 rctl = E1000_READ_REG(hw, E1000_RCTL);
1309 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1319 if (!e1000_tbi_sbp_enabled_82543(hw)) {
1320 e1000_set_tbi_sbp_82543(hw, TRUE);
1321 rctl = E1000_READ_REG(hw, E1000_RCTL);
1323 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1333 * @hw: pointer to the HW structure
1338 static s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw)
1340 struct e1000_mac_info *mac = &hw->mac;
1346 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1347 status = E1000_READ_REG(hw, E1000_STATUS);
1348 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1370 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
1373 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1375 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1378 ret_val = e1000_config_fc_after_link_up_generic(hw);
1391 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1392 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
1403 * @hw: pointer to the HW structure
1408 static s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw)
1416 if (!(hw->phy.ops.read_reg))
1420 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1428 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1436 hw->mac.ops.config_collision_dist(hw);
1447 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1455 * @hw: pointer to the HW structure
1462 static void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, u32 value)
1468 if ((hw->mac.type == e1000_82544) && (offset & 1)) {
1469 temp = E1000_READ_REG_ARRAY(hw, E1000_VFTA, offset - 1);
1470 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
1471 E1000_WRITE_FLUSH(hw);
1472 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset - 1, temp);
1473 E1000_WRITE_FLUSH(hw);
1475 e1000_write_vfta_generic(hw, offset, value);
1481 * @hw: pointer to the HW structure
1485 static s32 e1000_led_on_82543(struct e1000_hw *hw)
1487 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1491 if (hw->mac.type == e1000_82544 &&
1492 hw->phy.media_type == e1000_media_type_copper) {
1501 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1508 * @hw: pointer to the HW structure
1512 static s32 e1000_led_off_82543(struct e1000_hw *hw)
1514 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1518 if (hw->mac.type == e1000_82544 &&
1519 hw->phy.media_type == e1000_media_type_copper) {
1527 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1534 * @hw: pointer to the HW structure
1538 static void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw)
1542 e1000_clear_hw_cntrs_base_generic(hw);
1544 E1000_READ_REG(hw, E1000_PRC64);
1545 E1000_READ_REG(hw, E1000_PRC127);
1546 E1000_READ_REG(hw, E1000_PRC255);
1547 E1000_READ_REG(hw, E1000_PRC511);
1548 E1000_READ_REG(hw, E1000_PRC1023);
1549 E1000_READ_REG(hw, E1000_PRC1522);
1550 E1000_READ_REG(hw, E1000_PTC64);
1551 E1000_READ_REG(hw, E1000_PTC127);
1552 E1000_READ_REG(hw, E1000_PTC255);
1553 E1000_READ_REG(hw, E1000_PTC511);
1554 E1000_READ_REG(hw, E1000_PTC1023);
1555 E1000_READ_REG(hw, E1000_PTC1522);
1557 E1000_READ_REG(hw, E1000_ALGNERRC);
1558 E1000_READ_REG(hw, E1000_RXERRC);
1559 E1000_READ_REG(hw, E1000_TNCRS);
1560 E1000_READ_REG(hw, E1000_CEXTERR);
1561 E1000_READ_REG(hw, E1000_TSCTC);
1562 E1000_READ_REG(hw, E1000_TSCTFC);
1567 * @hw: pointer to the HW structure
1574 s32 e1000_read_mac_addr_82543(struct e1000_hw *hw)
1583 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
1588 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
1589 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
1593 if (hw->bus.func == E1000_FUNC_1)
1594 hw->mac.perm_addr[5] ^= 1;
1597 hw->mac.addr[i] = hw->mac.perm_addr[i];