Lines Matching refs:wptr
294 * GPU is currently reading, and a wptr (write pointer)
298 * wptr. The GPU then starts fetching commands and executes
320 ring->ring[ring->wptr++] = v;
321 ring->wptr &= ring->ptr_mask;
369 ring->ring_free_dw -= ring->wptr;
406 ring->wptr_old = ring->wptr;
441 * Update the wptr (write pointer) to tell the GPU to
447 while (ring->wptr & ring->align_mask) {
451 WREG32(ring->wptr_reg, (ring->wptr << ring->ptr_reg_shift) & ring->ptr_reg_mask);
471 * radeon_ring_undo - reset the wptr
475 * Reset the driver's copy of the wptr (all asics).
479 ring->wptr = ring->wptr_old;
483 * radeon_ring_unlock_undo - reset the wptr and unlock the ring
509 if (ring->rptr == ring->wptr) {
617 size = ring->wptr + (ring->ring_size / 4);
680 * @wptr_reg: MMIO offset of the wptr register
681 * @ptr_reg_shift: bit offset of the rptr/wptr values
682 * @ptr_reg_mask: bit mask of the rptr/wptr values
799 seq_printf(m, "wptr(0x%04x): 0x%08x [%5d]\n", ring->wptr_reg, tmp, tmp);
806 seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n", ring->wptr, ring->wptr);