Lines Matching refs:pm
60 for (i = 0; i < rdev->pm.num_power_states; i++) {
61 if (rdev->pm.power_state[i].type == ps_type) {
68 return rdev->pm.default_power_state_index;
73 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
74 if (rdev->pm.profile == PM_PROFILE_AUTO) {
75 sx_xlock(&rdev->pm.mutex);
78 sx_xunlock(&rdev->pm.mutex);
85 switch (rdev->pm.profile) {
87 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
92 if (rdev->pm.active_crtc_count > 1)
93 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
95 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
97 if (rdev->pm.active_crtc_count > 1)
98 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
100 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
105 if (rdev->pm.active_crtc_count > 1)
106 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
108 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
111 if (rdev->pm.active_crtc_count > 1)
112 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
114 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
117 if (rdev->pm.active_crtc_count > 1)
118 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
120 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
124 if (rdev->pm.active_crtc_count == 0) {
125 rdev->pm.requested_power_state_index =
126 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
127 rdev->pm.requested_clock_mode_index =
128 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
130 rdev->pm.requested_power_state_index =
131 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
132 rdev->pm.requested_clock_mode_index =
133 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
152 if (rdev->pm.active_crtcs) {
153 rdev->pm.vblank_sync = false;
156 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
167 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
168 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
172 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
173 clock_info[rdev->pm.requested_clock_mode_index].sclk;
174 if (sclk > rdev->pm.default_sclk)
175 sclk = rdev->pm.default_sclk;
181 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
183 rdev->pm.active_crtc_count &&
184 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
185 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
186 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
187 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
189 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
190 clock_info[rdev->pm.requested_clock_mode_index].mclk;
192 if (mclk > rdev->pm.default_mclk)
193 mclk = rdev->pm.default_mclk;
196 if (sclk < rdev->pm.current_sclk)
201 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
213 if (sclk != rdev->pm.current_sclk) {
217 rdev->pm.current_sclk = sclk;
222 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
226 rdev->pm.current_mclk = mclk;
236 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
237 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
239 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
247 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
248 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
252 sx_xlock(&rdev->pm.mclk_lock);
265 sx_xunlock(&rdev->pm.mclk_lock);
275 if (rdev->pm.active_crtcs & (1 << i)) {
276 rdev->pm.req_vblank |= (1 << i);
286 if (rdev->pm.req_vblank & (1 << i)) {
287 rdev->pm.req_vblank &= ~(1 << i);
295 if (rdev->pm.active_crtc_count)
298 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
301 sx_xunlock(&rdev->pm.mclk_lock);
311 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
312 for (i = 0; i < rdev->pm.num_power_states; i++) {
313 power_state = &rdev->pm.power_state[i];
316 if (i == rdev->pm.default_power_state_index)
346 int cp = rdev->pm.profile;
363 sx_xlock(&rdev->pm.mutex);
364 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
366 rdev->pm.profile = PM_PROFILE_DEFAULT;
368 rdev->pm.profile = PM_PROFILE_AUTO;
370 rdev->pm.profile = PM_PROFILE_LOW;
372 rdev->pm.profile = PM_PROFILE_MID;
374 rdev->pm.profile = PM_PROFILE_HIGH;
385 sx_xunlock(&rdev->pm.mutex);
396 int pm = rdev->pm.pm_method;
399 (pm == PM_METHOD_DYNPM) ? "dynpm" : "profile");
412 sx_xlock(&rdev->pm.mutex);
413 rdev->pm.pm_method = PM_METHOD_DYNPM;
414 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
415 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
416 sx_xunlock(&rdev->pm.mutex);
418 sx_xlock(&rdev->pm.mutex);
420 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
421 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
422 rdev->pm.pm_method = PM_METHOD_PROFILE;
423 sx_xunlock(&rdev->pm.mutex);
425 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
447 switch (rdev->pm.int_thermal_type) {
498 rdev->pm.int_hwmon_dev = NULL;
501 switch (rdev->pm.int_thermal_type) {
512 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
513 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
514 err = PTR_ERR(rdev->pm.int_hwmon_dev);
519 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev);
520 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj,
539 if (rdev->pm.int_hwmon_dev) {
540 sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup);
541 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
548 sx_xlock(&rdev->pm.mutex);
549 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
550 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
551 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
553 sx_xunlock(&rdev->pm.mutex);
556 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
566 if (rdev->pm.default_vddc)
567 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
569 if (rdev->pm.default_vddci)
570 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
572 if (rdev->pm.default_sclk)
573 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
574 if (rdev->pm.default_mclk)
575 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
578 sx_xlock(&rdev->pm.mutex);
579 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
580 rdev->pm.current_clock_mode_index = 0;
581 rdev->pm.current_sclk = rdev->pm.default_sclk;
582 rdev->pm.current_mclk = rdev->pm.default_mclk;
583 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
584 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
585 if (rdev->pm.pm_method == PM_METHOD_DYNPM
586 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
587 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
589 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
593 sx_xunlock(&rdev->pm.mutex);
602 rdev->pm.pm_method = PM_METHOD_PROFILE;
603 rdev->pm.profile = PM_PROFILE_DEFAULT;
604 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
605 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
606 rdev->pm.dynpm_can_upclock = true;
607 rdev->pm.dynpm_can_downclock = true;
608 rdev->pm.default_sclk = rdev->clock.default_sclk;
609 rdev->pm.default_mclk = rdev->clock.default_mclk;
610 rdev->pm.current_sclk = rdev->clock.default_sclk;
611 rdev->pm.current_mclk = rdev->clock.default_mclk;
612 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
625 if (rdev->pm.default_vddc)
626 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
628 if (rdev->pm.default_vddci)
629 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
631 if (rdev->pm.default_sclk)
632 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
633 if (rdev->pm.default_mclk)
634 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
644 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
647 if (rdev->pm.num_power_states > 1) {
672 if (rdev->pm.num_power_states > 1) {
674 sx_xlock(&rdev->pm.mutex);
675 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
676 rdev->pm.profile = PM_PROFILE_DEFAULT;
679 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
681 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
682 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
685 sx_xunlock(&rdev->pm.mutex);
689 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
696 if (rdev->pm.power_state) {
698 for (i = 0; i < rdev->pm.num_power_states; ++i) {
699 free(rdev->pm.power_state[i].clock_info, DRM_MEM_DRIVER);
701 free(rdev->pm.power_state, DRM_MEM_DRIVER);
702 rdev->pm.power_state = NULL;
703 rdev->pm.num_power_states = 0;
715 if (rdev->pm.num_power_states < 2)
718 sx_xlock(&rdev->pm.mutex);
720 rdev->pm.active_crtcs = 0;
721 rdev->pm.active_crtc_count = 0;
726 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
727 rdev->pm.active_crtc_count++;
731 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
734 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
735 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
736 if (rdev->pm.active_crtc_count > 1) {
737 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
739 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
742 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
743 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
749 } else if (rdev->pm.active_crtc_count == 1) {
752 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
753 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
754 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
759 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
762 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
763 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
765 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
771 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
773 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
776 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
777 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
785 sx_xunlock(&rdev->pm.mutex);
797 if (rdev->pm.active_crtcs & (1 << crtc)) {
814 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
825 pm.dynpm_idle_work.work);
828 sx_xlock(&rdev->pm.mutex);
829 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
844 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
845 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
846 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
847 rdev->pm.dynpm_can_upclock) {
848 rdev->pm.dynpm_planned_action =
850 rdev->pm.dynpm_action_timeout = jiffies +
854 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
855 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
856 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
857 rdev->pm.dynpm_can_downclock) {
858 rdev->pm.dynpm_planned_action =
860 rdev->pm.dynpm_action_timeout = jiffies +
868 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
869 jiffies > rdev->pm.dynpm_action_timeout) {
874 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
877 sx_xunlock(&rdev->pm.mutex);
893 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
895 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
896 if (rdev->asic->pm.get_memory_clock)
898 if (rdev->pm.current_vddc)
899 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
900 if (rdev->asic->pm.get_pcie_lanes)