drm2/radeon/radeon_combios.c

2686 	int state_index = 0;
2784 			rdev->pm.power_state[state_index].num_clock_modes = 1;
2785 			rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2786 			rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2787 			if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2788 			    (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2790 			rdev->pm.power_state[state_index].type =
2795 			rdev->pm.power_state[state_index].misc = misc;
2796 			rdev->pm.power_state[state_index].misc2 = misc2;
2798 				rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2800 					rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2803 					rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2805 				rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2807 					rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2810 					rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2815 						rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2818 						rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2820 						rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2825 					rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2828 					rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2831 					rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2834 					rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2837 					rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2841 				rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2843 				rdev->pm.power_state[state_index].pcie_lanes =
2845 			rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2846 			state_index++;
2856 	rdev->pm.power_state[state_index].type =
2858 	rdev->pm.power_state[state_index].num_clock_modes = 1;
2859 	rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2860 	rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2861 	rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2862 	if ((state_index > 0) &&
2864 		rdev->pm.power_state[state_index].clock_info[0].voltage =
2867 		rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2868 	rdev->pm.power_state[state_index].pcie_lanes = 16;
2869 	rdev->pm.power_state[state_index].flags = 0;
2870 	rdev->pm.default_power_state_index = state_index;
2871 	rdev->pm.num_power_states = state_index + 1;
2878 	rdev->pm.default_power_state_index = state_index;