Lines Matching defs:state_index
1937 int state_index,
1940 rdev->pm.power_state[state_index].misc = misc;
1941 rdev->pm.power_state[state_index].misc2 = misc2;
1944 rdev->pm.power_state[state_index].type =
1947 rdev->pm.power_state[state_index].type =
1950 rdev->pm.power_state[state_index].type =
1953 rdev->pm.power_state[state_index].type =
1956 rdev->pm.power_state[state_index].type =
1958 rdev->pm.power_state[state_index].flags &=
1962 rdev->pm.power_state[state_index].type =
1965 rdev->pm.power_state[state_index].type =
1967 rdev->pm.default_power_state_index = state_index;
1968 rdev->pm.power_state[state_index].default_clock_mode =
1969 &rdev->pm.power_state[state_index].clock_info[0];
1970 } else if (state_index == 0) {
1971 rdev->pm.power_state[state_index].clock_info[0].flags |=
1981 int state_index = 0;
1990 return state_index;
2018 return state_index;
2021 rdev->pm.power_state[state_index].clock_info =
2024 if (!rdev->pm.power_state[state_index].clock_info)
2025 return state_index;
2026 rdev->pm.power_state[state_index].num_clock_modes = 1;
2027 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2030 rdev->pm.power_state[state_index].clock_info[0].mclk =
2032 rdev->pm.power_state[state_index].clock_info[0].sclk =
2035 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2036 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2038 rdev->pm.power_state[state_index].pcie_lanes =
2043 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2045 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2049 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2052 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2055 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2057 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2060 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2061 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2062 state_index++;
2065 rdev->pm.power_state[state_index].clock_info[0].mclk =
2067 rdev->pm.power_state[state_index].clock_info[0].sclk =
2070 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2071 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2073 rdev->pm.power_state[state_index].pcie_lanes =
2079 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2081 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2085 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2088 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2091 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2093 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2096 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2097 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2098 state_index++;
2101 rdev->pm.power_state[state_index].clock_info[0].mclk =
2103 rdev->pm.power_state[state_index].clock_info[0].sclk =
2106 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2107 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2109 rdev->pm.power_state[state_index].pcie_lanes =
2115 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2117 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2121 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2124 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2127 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2129 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2132 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2134 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2138 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2139 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2140 state_index++;
2146 rdev->pm.power_state[state_index - 1].type =
2148 rdev->pm.default_power_state_index = state_index - 1;
2149 rdev->pm.power_state[state_index - 1].default_clock_mode =
2150 &rdev->pm.power_state[state_index - 1].clock_info[0];
2151 rdev->pm.power_state[state_index].flags &=
2153 rdev->pm.power_state[state_index].misc = 0;
2154 rdev->pm.power_state[state_index].misc2 = 0;
2156 return state_index;
2254 int state_index, int mode_index,
2264 rdev->pm.power_state[state_index].misc = misc;
2265 rdev->pm.power_state[state_index].misc2 = misc2;
2266 rdev->pm.power_state[state_index].pcie_lanes =
2271 rdev->pm.power_state[state_index].type =
2275 rdev->pm.power_state[state_index].type =
2279 rdev->pm.power_state[state_index].type =
2284 rdev->pm.power_state[state_index].type =
2288 rdev->pm.power_state[state_index].flags = 0;
2290 rdev->pm.power_state[state_index].flags |=
2293 rdev->pm.power_state[state_index].type =
2295 rdev->pm.default_power_state_index = state_index;
2296 rdev->pm.power_state[state_index].default_clock_mode =
2297 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2300 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2301 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2302 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2303 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2307 rdev->pm.power_state[state_index].clock_info[j].mclk =
2309 rdev->pm.power_state[state_index].clock_info[j].sclk =
2312 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2320 int state_index, int mode_index,
2330 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2334 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2341 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2342 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2343 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2345 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2347 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2354 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2355 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2356 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2358 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2360 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2367 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2368 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2369 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2371 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2376 switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) {
2382 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage,
2384 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2392 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2396 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2397 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2409 int state_index = 0, mode_index = 0;
2419 return state_index;
2427 return state_index;
2445 return state_index;
2454 state_index, mode_index,
2460 rdev->pm.power_state[state_index].clock_info[0].mclk =
2462 rdev->pm.power_state[state_index].clock_info[0].sclk =
2466 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2468 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2470 state_index++;
2474 for (i = 0; i < state_index; i++) {
2487 return state_index;
2496 int state_index = 0, mode_index = 0;
2509 return state_index;
2526 return state_index;
2539 return state_index;
2549 state_index, mode_index,
2555 rdev->pm.power_state[state_index].clock_info[0].mclk =
2557 rdev->pm.power_state[state_index].clock_info[0].sclk =
2561 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2563 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2565 state_index++;
2569 for (i = 0; i < state_index; i++) {
2582 return state_index;
2591 int state_index = 0;
2601 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2605 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2608 state_index = radeon_atombios_parse_power_table_6(rdev);
2622 rdev->pm.power_state[state_index].type =
2624 rdev->pm.power_state[state_index].num_clock_modes = 1;
2625 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2626 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2627 rdev->pm.power_state[state_index].default_clock_mode =
2628 &rdev->pm.power_state[state_index].clock_info[0];
2629 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2630 rdev->pm.power_state[state_index].pcie_lanes = 16;
2631 rdev->pm.default_power_state_index = state_index;
2632 rdev->pm.power_state[state_index].flags = 0;
2633 state_index++;
2638 rdev->pm.num_power_states = state_index;