drm2/radeon/evergreen_cs.c

1063  * evergreen_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1068  * @reloc:		reloc informations
1103 	/* FIXME: we assume reloc size is 4 dwords */
1136  * RELOC (P3) - crtc_id in reloc.
1228 			DRM_ERROR("unknown crtc reloc\n");
1245 			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1289 	struct radeon_cs_reloc *reloc;
1354 		r = evergreen_cs_packet_next_reloc(p, &reloc);
1360 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1383 			r = evergreen_cs_packet_next_reloc(p, &reloc);
1391 			ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1392 			track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1393 			if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1396 				evergreen_tiling_fields(reloc->lobj.tiling_flags,
1425 		r = evergreen_cs_packet_next_reloc(p, &reloc);
1432 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1433 		track->db_z_read_bo = reloc->robj;
1437 		r = evergreen_cs_packet_next_reloc(p, &reloc);
1444 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1445 		track->db_z_write_bo = reloc->robj;
1449 		r = evergreen_cs_packet_next_reloc(p, &reloc);
1456 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1457 		track->db_s_read_bo = reloc->robj;
1461 		r = evergreen_cs_packet_next_reloc(p, &reloc);
1468 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1469 		track->db_s_write_bo = reloc->robj;
1484 		r = evergreen_cs_packet_next_reloc(p, &reloc);
1492 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1493 		track->vgt_strmout_bo[tmp] = reloc->robj;
1506 		r = evergreen_cs_packet_next_reloc(p, &reloc);
1508 			dev_warn(p->dev, "missing reloc for CP_COHER_BASE "
1512 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1570 			r = evergreen_cs_packet_next_reloc(p, &reloc);
1576 			ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1577 			track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1588 			r = evergreen_cs_packet_next_reloc(p, &reloc);
1594 			ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1595 			track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1649 		r = evergreen_cs_packet_next_reloc(p, &reloc);
1656 			if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1659 				evergreen_tiling_fields(reloc->lobj.tiling_flags,
1677 		r = evergreen_cs_packet_next_reloc(p, &reloc);
1684 			if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1687 				evergreen_tiling_fields(reloc->lobj.tiling_flags,
1710 		r = evergreen_cs_packet_next_reloc(p, &reloc);
1715 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1716 		track->cb_color_fmask_bo[tmp] = reloc->robj;
1727 		r = evergreen_cs_packet_next_reloc(p, &reloc);
1732 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1733 		track->cb_color_cmask_bo[tmp] = reloc->robj;
1765 		r = evergreen_cs_packet_next_reloc(p, &reloc);
1773 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1774 		track->cb_color_bo[tmp] = reloc->robj;
1781 		r = evergreen_cs_packet_next_reloc(p, &reloc);
1789 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1790 		track->cb_color_bo[tmp] = reloc->robj;
1794 		r = evergreen_cs_packet_next_reloc(p, &reloc);
1801 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1802 		track->htile_bo = reloc->robj;
1912 		r = evergreen_cs_packet_next_reloc(p, &reloc);
1918 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1926 		r = evergreen_cs_packet_next_reloc(p, &reloc);
1932 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1940 		r = evergreen_cs_packet_next_reloc(p, &reloc);
1946 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1987 	struct radeon_cs_reloc *reloc;
2025 		r = evergreen_cs_packet_next_reloc(p, &reloc);
2031 		offset = reloc->lobj.gpu_offset +
2071 		r = evergreen_cs_packet_next_reloc(p, &reloc);
2077 		offset = reloc->lobj.gpu_offset +
2098 		r = evergreen_cs_packet_next_reloc(p, &reloc);
2104 		offset = reloc->lobj.gpu_offset +
2126 		r = evergreen_cs_packet_next_reloc(p, &reloc);
2132 		offset = reloc->lobj.gpu_offset +
2217 		r = evergreen_cs_packet_next_reloc(p, &reloc);
2222 		ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
2238 			r = evergreen_cs_packet_next_reloc(p, &reloc);
2244 			offset = reloc->lobj.gpu_offset +
2289 				r = evergreen_cs_packet_next_reloc(p, &reloc);
2298 				offset = reloc->lobj.gpu_offset + tmp;
2300 				if ((tmp + size) > radeon_bo_size(reloc->robj)) {
2302 						 (uintmax_t)tmp + size, radeon_bo_size(reloc->robj));
2327 				r = evergreen_cs_packet_next_reloc(p, &reloc);
2336 				offset = reloc->lobj.gpu_offset + tmp;
2338 				if ((tmp + size) > radeon_bo_size(reloc->robj)) {
2340 						 (uintmax_t)tmp + size, radeon_bo_size(reloc->robj));
2361 			r = evergreen_cs_packet_next_reloc(p, &reloc);
2366 			ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2377 			r = evergreen_cs_packet_next_reloc(p, &reloc);
2382 			offset = reloc->lobj.gpu_offset +
2398 		r = evergreen_cs_packet_next_reloc(p, &reloc);
2404 		offset = reloc->lobj.gpu_offset +
2420 		r = evergreen_cs_packet_next_reloc(p, &reloc);
2426 		offset = reloc->lobj.gpu_offset +
2487 				r = evergreen_cs_packet_next_reloc(p, &reloc);
2494 						TEX_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
2495 					if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
2498 						evergreen_tiling_fields(reloc->lobj.tiling_flags,
2509 				texture = reloc->robj;
2510 				toffset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2524 					r = evergreen_cs_packet_next_reloc(p, &reloc);
2529 					moffset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2530 					mipmap = reloc->robj;
2543 				r = evergreen_cs_packet_next_reloc(p, &reloc);
2550 				if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
2553 					ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj) - offset;
2556 				offset64 = reloc->lobj.gpu_offset + offset;
2625 			r = evergreen_cs_packet_next_reloc(p, &reloc);
2627 				DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n");
2632 			if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2634 					  (uintmax_t)offset + 4, radeon_bo_size(reloc->robj));
2637 			offset += reloc->lobj.gpu_offset;
2644 			r = evergreen_cs_packet_next_reloc(p, &reloc);
2646 				DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n");
2651 			if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2653 					  (uintmax_t)offset + 4, radeon_bo_size(reloc->robj));
2656 			offset += reloc->lobj.gpu_offset;
2669 		r = evergreen_cs_packet_next_reloc(p, &reloc);
2671 			DRM_ERROR("bad MEM_WRITE (missing reloc)\n");
2680 		if ((offset + 8) > radeon_bo_size(reloc->robj)) {
2682 				  (uintmax_t)offset + 8, radeon_bo_size(reloc->robj));
2685 		offset += reloc->lobj.gpu_offset;
2698 			r = evergreen_cs_packet_next_reloc(p, &reloc);
2700 				DRM_ERROR("bad COPY_DW (missing src reloc)\n");
2705 			if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2707 					  (uintmax_t)offset + 4, radeon_bo_size(reloc->robj));
2710 			offset += reloc->lobj.gpu_offset;
2722 			r = evergreen_cs_packet_next_reloc(p, &reloc);
2724 				DRM_ERROR("bad COPY_DW (missing dst reloc)\n");
2729 			if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2731 					  (uintmax_t)offset + 4, radeon_bo_size(reloc->robj));
2734 			offset += reloc->lobj.gpu_offset;
2880  * the GPU addresses based on the reloc information and