drm2/radeon/evergreen_cs.c

453 			volatile u32 *ib = p->ib.ptr;
475 						ib[track->cb_color_slice_idx[id]] = slice;
1016  * evergreen_cs_packet_parse() - parse cp packet and point ib index to next packet
1021  * if packet is bigger than remaining ib size. or if packets is unknown.
1152 	volatile uint32_t *ib;
1154 	ib = p->ib.ptr;
1212 		ib[h_idx + 2] = PACKET2(0);
1213 		ib[h_idx + 3] = PACKET2(0);
1214 		ib[h_idx + 4] = PACKET2(0);
1215 		ib[h_idx + 5] = PACKET2(0);
1216 		ib[h_idx + 6] = PACKET2(0);
1217 		ib[h_idx + 7] = PACKET2(0);
1218 		ib[h_idx + 8] = PACKET2(0);
1224 			ib[h_idx] = header;
1225 			ib[h_idx + 4] = (EVERGREEN_VLINE_STATUS + radeon_crtc->crtc_offset) >> 2;
1245 			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1291 	u32 m, i, tmp, *ib;
1312 	ib = p->ib.ptr;
1344 		  ib[idx] = 0;*/
1360 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1389 			ib[idx] &= ~Z_ARRAY_MODE(0xf);
1391 			ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1399 				ib[idx] |= DB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
1400 				ib[idx] |= DB_TILE_SPLIT(tile_split) |
1432 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1444 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1456 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1468 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1492 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1512 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1576 			ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1594 			ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1662 				ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
1663 				ib[idx] |= CB_TILE_SPLIT(tile_split) |
1670 		track->cb_color_attrib[tmp] = ib[idx];
1690 				ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
1691 				ib[idx] |= CB_TILE_SPLIT(tile_split) |
1698 		track->cb_color_attrib[tmp] = ib[idx];
1715 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1732 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1773 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1789 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1801 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1809 		ib[idx] |= 3;
1918 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1932 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1946 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1989 	volatile u32 *ib;
1997 	ib = p->ib.ptr;
2035 		ib[idx + 0] = offset;
2036 		ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff);
2081 		ib[idx+0] = offset;
2082 		ib[idx+1] = upper_32_bits(offset) & 0xff;
2108 		ib[idx+0] = offset;
2109 		ib[idx+1] = upper_32_bits(offset) & 0xff;
2136 		ib[idx+1] = offset;
2137 		ib[idx+2] = upper_32_bits(offset) & 0xff;
2222 		ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
2248 			ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffffc);
2249 			ib[idx+2] = upper_32_bits(offset) & 0xff;
2306 				ib[idx] = offset;
2307 				ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
2344 				ib[idx+2] = offset;
2345 				ib[idx+3] = upper_32_bits(offset) & 0xff;
2366 			ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2386 			ib[idx+1] = offset & 0xfffffff8;
2387 			ib[idx+2] = upper_32_bits(offset) & 0xff;
2408 		ib[idx+1] = offset & 0xfffffffc;
2409 		ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
2430 		ib[idx+1] = offset & 0xfffffffc;
2431 		ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
2493 					ib[idx+1+(i*8)+1] |=
2501 						ib[idx+1+(i*8)+6] |= TEX_TILE_SPLIT(tile_split);
2502 						ib[idx+1+(i*8)+7] |=
2513 				tex_dim = ib[idx+1+(i*8)+0] & 0x7;
2514 				mip_address = ib[idx+1+(i*8)+3];
2536 				ib[idx+1+(i*8)+2] += toffset;
2537 				ib[idx+1+(i*8)+3] += moffset;
2553 					ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj) - offset;
2557 				ib[idx+1+(i*8)+0] = offset64;
2558 				ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) |
2638 			ib[idx+1] = offset;
2639 			ib[idx+2] = upper_32_bits(offset) & 0xff;
2657 			ib[idx+3] = offset;
2658 			ib[idx+4] = upper_32_bits(offset) & 0xff;
2686 		ib[idx+0] = offset;
2687 		ib[idx+1] = upper_32_bits(offset) & 0xff;
2711 			ib[idx+1] = offset;
2712 			ib[idx+2] = upper_32_bits(offset) & 0xff;
2735 			ib[idx+3] = offset;
2736 			ib[idx+4] = upper_32_bits(offset) & 0xff;
2855 	for (r = 0; r < p->ib.length_dw; r++) {
2856 		DRM_INFO("%05d  0x%08X\n", r, p->ib.ptr[r]);
2889 	volatile u32 *ib = p->ib.ptr;
2919 				ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
2925 				ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
2926 				ib[idx+2] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
2982 						ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
2983 						ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset >> 8);
2984 						ib[idx+8] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
2985 						ib[idx+9] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
2997 							ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
2999 							ib[idx+7] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
3000 							ib[idx+8] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
3003 							ib[idx+7] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
3004 							ib[idx+8] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
3006 							ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
3042 						ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
3043 						ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset >> 8);
3044 						ib[idx+8] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
3045 						ib[idx+9] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
3055 							ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
3059 							ib[idx+7] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
3060 							ib[idx+8] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
3065 							ib[idx+7] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
3066 							ib[idx+8] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
3070 							ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
3090 						ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
3091 						ib[idx+4] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
3126 						ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
3127 						ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset >> 8);
3128 						ib[idx+8] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
3129 						ib[idx+9] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
3144 							ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
3148 							ib[idx+7] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
3149 							ib[idx+8] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
3154 							ib[idx+7] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
3155 							ib[idx+8] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
3159 							ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
3197 						ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xffffffff);
3198 						ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xffffffff);
3199 						ib[idx+3] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
3200 						ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
3209 						ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset & 0xffffffff);
3210 						ib[idx+2] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
3211 						ib[idx+4] += (u32)(dst_reloc->lobj.gpu_offset & 0xffffffff);
3212 						ib[idx+5] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
3244 						ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
3245 						ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset & 0xfffffffc);
3246 						ib[idx+3] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
3247 						ib[idx+4] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
3248 						ib[idx+5] += upper_32_bits(dst2_reloc->lobj.gpu_offset) & 0xff;
3249 						ib[idx+6] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
3272 					ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
3273 					ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
3274 					ib[idx+3] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
3275 					ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
3293 			ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
3294 			ib[idx+3] += (upper_32_bits(dst_reloc->lobj.gpu_offset) << 16) & 0x00ff0000;
3306 	for (r = 0; r < p->ib->length_dw; r++) {
3307 		DRM_INFO("%05d  0x%08X\n", r, p->ib.ptr[r]);
3438 				      u32 *ib, struct radeon_cs_packet *pkt)
3441 	u32 idx_value = ib[idx];
3491 			reg = ib[idx + 5] * 4;
3498 			reg = ib[idx + 3] * 4;
3519 		command = ib[idx + 4];
3520 		info = ib[idx + 1];
3557 				start_reg = ib[idx + 2];
3582 int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
3590 		pkt.type = CP_PACKET_GET_TYPE(ib->ptr[idx]);
3591 		pkt.count = CP_PACKET_GET_COUNT(ib->ptr[idx]);
3602 			pkt.opcode = CP_PACKET3_GET_OPCODE(ib->ptr[idx]);
3603 			ret = evergreen_vm_packet3_check(rdev, ib->ptr, &pkt);
3613 	} while (idx < ib->length_dw);
3621  * @ib:	radeon_ib pointer
3627 int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
3633 		header = ib->ptr[idx];
3724 	} while (idx < ib->length_dw);