drm2/i915/intel_display.c

475 	list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
476 		if (encoder->base.crtc == crtc && encoder->type == type)
1763 			dev_priv->cfb_fb = work->crtc->fb->base.id;
1930 	if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1971 	    dev_priv->cfb_fb == fb->base.id &&
2138 	DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2224 	DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2235 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2258 	struct drm_device *dev = obj->base.dev;
2335 		DRM_ERROR("failed to update base address\n");
2966 	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2967 		if (encoder->base.crtc != crtc)
2972 			if (!intel_encoder_is_pch_edp(&encoder->base))
3276 		struct drm_device *dev = intel_crtc->base.dev;
3497 	struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
5213 	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5214 		if (encoder->base.crtc != crtc)
5566 			    base.head) {
5574 			if (intel_encoder_is_pch_edp(&encoder->base))
5675 	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5676 		if (encoder->base.crtc != crtc)
5727 	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5728 		if (encoder->base.crtc != crtc)
5815 	    !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5822 		if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5913 	if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5959 		    intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
6037 	if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
6049 	     intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
6128 	    !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
6338 			 connector->base.id,
6340 			 connector->encoder->base.id,
6374 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6379 	bool visible = base != 0;
6387 		/* On these chipsets we can only modify the base whilst
6390 		I915_WRITE(_CURABASE, base);
6404 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6410 	bool visible = base != 0;
6414 		if (base) {
6427 	I915_WRITE(CURBASE(pipe), base);
6430 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6436 	bool visible = base != 0;
6440 		if (base) {
6452 	I915_WRITE(CURBASE_IVB(pipe), base);
6465 	u32 base, pos;
6471 		base = intel_crtc->cursor_addr;
6473 			base = 0;
6476 			base = 0;
6478 		base = 0;
6482 			base = 0;
6491 			base = 0;
6498 	visible = base != 0;
6504 		ivb_update_cursor(crtc, base);
6508 			i845_update_cursor(crtc, base);
6510 			i9xx_update_cursor(crtc, base);
6547 	if (&obj->base == NULL)
6550 	if (obj->base.size < width * height * 4) {
6600 		drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6618 	drm_gem_object_unreference_unlocked(&obj->base);
6701 		drm_gem_object_unreference_unlocked(&obj->base);
6706 	*res = &intel_fb->base;
6765 	fb = &dev_priv->fbdev->ifb.base;
6772 	if (obj->base.size < mode->vdisplay * fb->pitches[0]) {
6788 	struct drm_encoder *encoder = &intel_encoder->base;
6795 		      connector->base.id, drm_get_connector_name(connector),
6796 		      encoder->base.id, drm_get_encoder_name(encoder));
6902 	struct drm_encoder *encoder = &intel_encoder->base;
6909 		      connector->base.id, drm_get_connector_name(connector),
6910 		      encoder->base.id, drm_get_encoder_name(encoder));
7070 	struct drm_crtc *crtc = &intel_crtc->base;
7267 	drm_gem_object_unreference(&work->pending_flip_obj->base);
7268 	drm_gem_object_unreference(&work->old_fb_obj->base);
7326 		list_add_tail(&e->base.link,
7327 			      &e->base.file_priv->event_list);
7328 		drm_event_wakeup(&e->base);
7413 	OUT_RING(0); /* aux display base address, unused */
7478 	 * so we need only reprogram the base address.
7618 	drm_gem_object_reference(&work->old_fb_obj->base);
7619 	drm_gem_object_reference(&obj->base);
7644 	drm_gem_object_unreference(&work->old_fb_obj->base);
7645 	drm_gem_object_unreference(&obj->base);
7747 	drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7749 	drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7767 	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7768 	dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7770 	intel_crtc_reset(&intel_crtc->base);
7784 	drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7824 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7961 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7962 		encoder->base.possible_crtcs = encoder->crtc_mask;
7963 		encoder->base.possible_clones =
7979 	drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7991 	return drm_gem_handle_create(file, &obj->base, handle);
8033 	ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8039 	drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8053 	if (&obj->base == NULL)
8095 	drm_gem_object_unreference(&ctx->base);
8843 		drm_gem_object_unreference(&dev_priv->renderctx->base);
8849 		drm_gem_object_unreference(&dev_priv->pwrctx->base);
9298 	dev->mode_config.fb_base = dev->agp->base;
9397 	return &intel_attached_encoder(connector)->base;
9404 	drm_mode_connector_attach_encoder(&connector->base,
9405 					  &encoder->base);
9432 		u32 base;
9473 		error->cursor[i].base = I915_READ(CURBASE(i));
9530 		sbuf_printf(m, "  BASE: %08x\n", error->cursor[i].base);