dev/amd/amd.c

514 		struct ccb_trans_settings_spi *spi =
515 		    &cts->xport_specific.spi;
526 				spi->flags = CTS_SPI_FLAGS_DISC_ENB;
528 				spi->flags = 0;
539 				spi->flags = CTS_SPI_FLAGS_DISC_ENB;
541 				spi->flags = 0;
550 		spi->sync_period = tinfo->period;
551 		spi->sync_offset = tinfo->offset;
554 		spi->bus_width = MSG_EXT_WDTR_BUS_8_BIT;
555 		spi->valid = CTS_SPI_VALID_SYNC_RATE
575 		struct ccb_trans_settings_spi *spi =
576 		    &cts->xport_specific.spi;
591 		if ((spi->valid & CTS_SPI_VALID_DISC) != 0) {
593 				if ((spi->flags & CTS_SPI_FLAGS_DISC_ENB)
601 				if ((spi->flags & CTS_SPI_FLAGS_DISC_ENB)
628 		if ((spi->valid & CTS_SPI_VALID_SYNC_OFFSET) == 0) {
630 				spi->sync_offset = targ_info->goal.offset;
632 				spi->sync_offset = targ_info->user.offset;
635 		if (spi->sync_offset > AMD_MAX_SYNC_OFFSET)
636 			spi->sync_offset = AMD_MAX_SYNC_OFFSET;
638 		if ((spi->valid & CTS_SPI_VALID_SYNC_RATE) == 0) {
640 				spi->sync_period = targ_info->goal.period;
642 				spi->sync_period = targ_info->user.period;
646 		if ((spi->sync_period != 0)
647 		 && (spi->sync_period < tinfo_sync_period[0]))
648 			spi->sync_period = tinfo_sync_period[0];
649 		if (spi->sync_period > tinfo_sync_period[last_entry])
650 		 	spi->sync_period = 0;
651 		if (spi->sync_offset == 0)
652 			spi->sync_period = 0;
655 			targ_info->user.period = spi->sync_period;
656 			targ_info->user.offset = spi->sync_offset;
659 			targ_info->goal.period = spi->sync_period;
660 			targ_info->goal.offset = spi->sync_offset;
804 			struct ccb_trans_settings_spi *spi =
805 			    &neg.xport_specific.spi;
808 			spi->sync_period = period;
809 			spi->sync_offset = offset;
810 			spi->valid = CTS_SPI_VALID_SYNC_RATE