Lines Matching refs:adv
197 static void adv_read_lram_16_multi(struct adv_softc *adv, u_int16_t s_addr,
199 static void adv_write_lram_16_multi(struct adv_softc *adv,
202 static void adv_mset_lram_16(struct adv_softc *adv, u_int16_t s_addr,
204 static u_int32_t adv_msum_lram_16(struct adv_softc *adv, u_int16_t s_addr,
207 static int adv_write_and_verify_lram_16(struct adv_softc *adv,
209 static u_int32_t adv_read_lram_32(struct adv_softc *adv, u_int16_t addr);
212 static void adv_write_lram_32(struct adv_softc *adv, u_int16_t addr,
214 static void adv_write_lram_32_multi(struct adv_softc *adv,
219 static u_int16_t adv_read_eeprom_16(struct adv_softc *adv, u_int8_t addr);
220 static u_int16_t adv_write_eeprom_16(struct adv_softc *adv, u_int8_t addr,
222 static int adv_write_eeprom_cmd_reg(struct adv_softc *adv,
224 static int adv_set_eeprom_config_once(struct adv_softc *adv,
228 static u_int32_t adv_load_microcode(struct adv_softc *adv, u_int16_t s_addr,
231 static void adv_reinit_lram(struct adv_softc *adv);
232 static void adv_init_lram(struct adv_softc *adv);
233 static int adv_init_microcode_var(struct adv_softc *adv);
234 static void adv_init_qlink_var(struct adv_softc *adv);
237 static void adv_disable_interrupt(struct adv_softc *adv);
238 static void adv_enable_interrupt(struct adv_softc *adv);
239 static void adv_toggle_irq_act(struct adv_softc *adv);
242 static int adv_host_req_chip_halt(struct adv_softc *adv);
243 static void adv_set_chip_ih(struct adv_softc *adv, u_int16_t ins_code);
245 static u_int8_t adv_get_chip_scsi_ctrl(struct adv_softc *adv);
267 static void adv_get_q_info(struct adv_softc *adv, u_int16_t s_addr,
269 static u_int adv_get_num_free_queues(struct adv_softc *adv, u_int8_t n_qs);
270 static u_int8_t adv_alloc_free_queues(struct adv_softc *adv,
272 static u_int8_t adv_alloc_free_queue(struct adv_softc *adv,
274 static int adv_send_scsi_queue(struct adv_softc *adv,
277 static void adv_put_ready_sg_list_queue(struct adv_softc *adv,
280 static void adv_put_ready_queue(struct adv_softc *adv,
282 static void adv_put_scsiq(struct adv_softc *adv, u_int16_t s_addr,
286 static void adv_handle_extmsg_in(struct adv_softc *adv,
290 static void adv_msgout_sdtr(struct adv_softc *adv, u_int8_t sdtr_period,
292 static void adv_set_sdtr_reg_at_id(struct adv_softc *adv, int id,
301 struct adv_softc *adv;
303 adv = (struct adv_softc *)callback_arg;
304 mtx_assert(&adv->lock, MA_OWNED);
330 if (adv->bug_fix_control & ADV_BUG_FIX_ASYN_USE_SYN) {
332 adv->fix_asyn_xfer_always |= target_mask;
334 adv->fix_asyn_xfer_always &= ~target_mask;
345 adv->fix_asyn_xfer &= ~target_mask;
351 tinfo = &adv->tinfo[cgd->ccb_h.target_id];
352 adv_set_syncrate(adv, cgd->ccb_h.path,
363 if (adv->bug_fix_control & ADV_BUG_FIX_ASYN_USE_SYN) {
365 adv->fix_asyn_xfer |= target_mask;
372 adv_set_syncrate(adv, /*path*/NULL,
384 adv_set_bank(struct adv_softc *adv, u_int8_t bank)
391 control = ADV_INB(adv, ADV_CHIP_CTRL)
400 ADV_OUTB(adv, ADV_CHIP_CTRL, control);
404 adv_read_lram_8(struct adv_softc *adv, u_int16_t addr)
412 ADV_OUTW(adv, ADV_LRAM_ADDR, addr & 0xFFFE);
413 word_data = ADV_INW(adv, ADV_LRAM_DATA);
431 adv_write_lram_8(struct adv_softc *adv, u_int16_t addr, u_int8_t value)
435 word_data = adv_read_lram_16(adv, addr & 0xFFFE);
443 adv_write_lram_16(adv, addr & 0xFFFE, word_data);
448 adv_read_lram_16(struct adv_softc *adv, u_int16_t addr)
450 ADV_OUTW(adv, ADV_LRAM_ADDR, addr);
451 return (ADV_INW(adv, ADV_LRAM_DATA));
455 adv_write_lram_16(struct adv_softc *adv, u_int16_t addr, u_int16_t value)
457 ADV_OUTW(adv, ADV_LRAM_ADDR, addr);
458 ADV_OUTW(adv, ADV_LRAM_DATA, value);
481 adv_lib_init(struct adv_softc *adv)
483 if ((adv->type & ADV_ULTRA) != 0) {
484 adv->sdtr_period_tbl = adv_sdtr_period_tbl_ultra;
485 adv->sdtr_period_tbl_size = sizeof(adv_sdtr_period_tbl_ultra);
487 adv->sdtr_period_tbl = adv_sdtr_period_tbl;
488 adv->sdtr_period_tbl_size = sizeof(adv_sdtr_period_tbl);
493 adv_get_eeprom_config(struct adv_softc *adv, struct
506 *wbuf = adv_read_eeprom_16(adv, s_addr);
510 if (adv->type & ADV_VL) {
519 *wbuf = adv_read_eeprom_16(adv, s_addr);
525 *wbuf = adv_read_eeprom_16(adv, s_addr);
530 adv_set_eeprom_config(struct adv_softc *adv,
537 if (adv_set_eeprom_config_once(adv, eeprom_config) == 0) {
548 adv_reset_chip(struct adv_softc *adv, int reset_bus)
550 adv_stop_chip(adv);
551 ADV_OUTB(adv, ADV_CHIP_CTRL, ADV_CC_CHIP_RESET | ADV_CC_HALT
555 adv_set_chip_ih(adv, ADV_INS_RFLAG_WTM);
556 adv_set_chip_ih(adv, ADV_INS_HALT);
559 ADV_OUTB(adv, ADV_CHIP_CTRL, ADV_CC_CHIP_RESET | ADV_CC_HALT);
561 ADV_OUTB(adv, ADV_CHIP_CTRL, ADV_CC_HALT);
565 ADV_OUTW(adv, ADV_CHIP_STATUS, ADV_CIW_CLR_SCSI_RESET_INT);
566 ADV_OUTW(adv, ADV_CHIP_STATUS, 0);
567 return (adv_is_chip_halted(adv));
571 adv_test_external_lram(struct adv_softc* adv)
580 saved_value = adv_read_lram_16(adv, q_addr);
581 if (adv_write_and_verify_lram_16(adv, q_addr, 0x55AA) == 0) {
583 adv_write_lram_16(adv, q_addr, saved_value);
590 adv_init_lram_and_mcode(struct adv_softc *adv)
594 adv_disable_interrupt(adv);
596 adv_init_lram(adv);
598 retval = adv_load_microcode(adv, 0, (u_int16_t *)adv_mcode,
601 device_printf(adv->dev,
606 if (adv_init_microcode_var(adv) != 0)
609 adv_enable_interrupt(adv);
614 adv_get_chip_irq(struct adv_softc *adv)
619 cfg_lsw = ADV_INW(adv, ADV_CONFIG_LSW);
621 if ((adv->type & ADV_VL) != 0) {
637 adv_set_chip_irq(struct adv_softc *adv, u_int8_t irq_no)
641 if ((adv->type & ADV_VL) != 0) {
650 cfg_lsw = ADV_INW(adv, ADV_CONFIG_LSW) & 0xFFE3;
652 ADV_OUTW(adv, ADV_CONFIG_LSW, cfg_lsw);
653 adv_toggle_irq_act(adv);
655 cfg_lsw = ADV_INW(adv, ADV_CONFIG_LSW) & 0xFFE0;
657 ADV_OUTW(adv, ADV_CONFIG_LSW, cfg_lsw);
658 adv_toggle_irq_act(adv);
659 } else if ((adv->type & ADV_ISA) != 0) {
663 cfg_lsw = ADV_INW(adv, ADV_CONFIG_LSW) & 0xFFF3;
665 ADV_OUTW(adv, ADV_CONFIG_LSW, cfg_lsw);
667 return (adv_get_chip_irq(adv));
671 adv_set_chip_scsiid(struct adv_softc *adv, int new_id)
675 cfg_lsw = ADV_INW(adv, ADV_CONFIG_LSW);
680 ADV_OUTW(adv, ADV_CONFIG_LSW, cfg_lsw);
684 adv_execute_scsi_queue(struct adv_softc *adv, struct adv_scsi_q *scsiq,
700 mtx_assert(&adv->lock, MA_OWNED);
705 tinfo = &adv->tinfo[tid_no];
709 adv_set_syncrate(adv, /*struct cam_path */NULL,
713 adv_msgout_sdtr(adv, tinfo->goal.period,
732 if ((adv->type & (ADV_ISA | ADV_VL | ADV_EISA)) != 0) {
760 if ((adv->fix_asyn_xfer & scsiq->q1.target_id) != 0
761 && (adv->fix_asyn_xfer_always & scsiq->q1.target_id) == 0) {
788 if ((adv->bug_fix_control & ADV_BUG_FIX_IF_NOT_DWB) != 0
803 if ((adv_get_num_free_queues(adv, n_q_required) >= n_q_required)
805 retval = adv_send_scsi_queue(adv, scsiq, n_q_required);
812 adv_copy_lram_doneq(struct adv_softc *adv, u_int16_t q_addr,
818 adv_get_q_info(adv, q_addr + ADV_SCSIQ_DONE_INFO_BEG,
826 val = adv_read_lram_16(adv, q_addr + ADV_SCSIQ_B_STATUS);
830 val = adv_read_lram_16(adv, q_addr + ADV_SCSIQ_B_CNTL);
834 val = adv_read_lram_16(adv,q_addr + ADV_SCSIQ_B_SENSE_LEN);
843 adv_read_lram_16(adv, q_addr + ADV_SCSIQ_DW_REMAIN_XFER_CNT);
845 adv_read_lram_16(adv, q_addr + ADV_SCSIQ_W_ALT_DC1) << 16;
857 adv_start_chip(struct adv_softc *adv)
859 ADV_OUTB(adv, ADV_CHIP_CTRL, 0);
860 if ((ADV_INW(adv, ADV_CHIP_STATUS) & ADV_CSW_HALTED) != 0)
866 adv_stop_execution(struct adv_softc *adv)
871 if (adv_read_lram_8(adv, ADV_STOP_CODE_B) == 0) {
872 adv_write_lram_8(adv, ADV_STOP_CODE_B,
875 if (adv_read_lram_8(adv, ADV_STOP_CODE_B) &
886 adv_is_chip_halted(struct adv_softc *adv)
888 if ((ADV_INW(adv, ADV_CHIP_STATUS) & ADV_CSW_HALTED) != 0) {
889 if ((ADV_INB(adv, ADV_CHIP_CTRL) & ADV_CC_HALT) != 0) {
901 adv_ack_interrupt(struct adv_softc *adv)
909 risc_flag = adv_read_lram_8(adv, ADVV_RISC_FLAG_B);
915 host_flag = adv_read_lram_8(adv, ADVV_HOST_FLAG_B);
916 adv_write_lram_8(adv, ADVV_HOST_FLAG_B,
919 ADV_OUTW(adv, ADV_CHIP_STATUS, ADV_CIW_INT_ACK);
921 while (ADV_INW(adv, ADV_CHIP_STATUS) & ADV_CSW_INT_PENDING) {
922 ADV_OUTW(adv, ADV_CHIP_STATUS, ADV_CIW_INT_ACK);
928 adv_write_lram_8(adv, ADVV_HOST_FLAG_B, host_flag);
936 adv_isr_chip_halted(struct adv_softc *adv)
948 mtx_assert(&adv->lock, MA_OWNED);
949 int_halt_code = adv_read_lram_16(adv, ADVV_HALTCODE_W);
950 halt_qp = adv_read_lram_8(adv, ADVV_CURCDB_B);
952 target_ix = adv_read_lram_8(adv, halt_q_addr + ADV_SCSIQ_B_TARGET_IX);
953 q_cntl = adv_read_lram_8(adv, halt_q_addr + ADV_SCSIQ_B_CNTL);
963 adv->fix_asyn_xfer &= ~target_mask;
964 adv_set_syncrate(adv, /*struct cam_path */NULL,
967 adv->fix_asyn_xfer |= target_mask;
969 adv_set_syncrate(adv, /*struct cam_path */NULL,
973 adv_handle_extmsg_in(adv, halt_q_addr, q_cntl,
983 tinfo = &adv->tinfo[tid_no];
987 adv_set_syncrate(adv, /*struct cam_path */NULL,
991 adv_msgout_sdtr(adv, tinfo->goal.period,
995 adv_write_lram_8(adv, halt_q_addr + ADV_SCSIQ_B_CNTL, q_cntl);
998 tag_code = adv_read_lram_8(adv,
1003 if ((adv->fix_asyn_xfer & target_mask) != 0
1004 && (adv->fix_asyn_xfer_always & target_mask) == 0) {
1008 adv_write_lram_8(adv, halt_q_addr + ADV_SCSIQ_B_TAG_CODE,
1010 q_status = adv_read_lram_8(adv,
1013 adv_write_lram_8(adv, halt_q_addr + ADV_SCSIQ_B_STATUS,
1019 adv_read_lram_32(adv, halt_q_addr + ADV_SCSIQ_D_CINFO_IDX);
1020 cinfo = &adv->ccb_infos[cinfo_index];
1021 ccb = adv->ccb_infos[cinfo_index].ccb;
1024 adv_abort_ccb(adv, tid_no, ADV_TIX_TO_LUN(target_ix),
1027 scsi_busy = adv_read_lram_8(adv, ADVV_SCSIBUSY_B);
1029 adv_write_lram_8(adv, ADVV_SCSIBUSY_B, scsi_busy);
1038 adv_read_lram_16_multi(adv, ADVV_MSGOUT_BEG,
1047 adv_set_syncrate(adv, /*struct cam_path */NULL,
1052 adv_write_lram_8(adv, halt_q_addr + ADV_SCSIQ_B_CNTL, q_cntl);
1058 scsi_status = adv_read_lram_8(adv, halt_q_addr
1061 adv_read_lram_32(adv, halt_q_addr + ADV_SCSIQ_D_CINFO_IDX);
1062 ccb = adv->ccb_infos[cinfo_index].ccb;
1066 adv_abort_ccb(adv, tid_no, ADV_TIX_TO_LUN(target_ix),
1069 scsi_busy = adv_read_lram_8(adv, ADVV_SCSIBUSY_B);
1071 adv_write_lram_8(adv, ADVV_SCSIBUSY_B, scsi_busy);
1075 adv_write_lram_16(adv, ADVV_HALTCODE_W, 0);
1079 adv_sdtr_to_period_offset(struct adv_softc *adv,
1083 if (adv->fix_asyn_xfer & ADV_TID_TO_TARGET_MASK(tid)
1087 *period = adv->sdtr_period_tbl[((sync_data >> 4) & 0xF)];
1093 adv_set_syncrate(struct adv_softc *adv, struct cam_path *path,
1101 mtx_assert(&adv->lock, MA_OWNED);
1102 tinfo = &adv->tinfo[tid];
1105 sdtr_data = adv_period_offset_to_sdtr(adv, &period,
1116 halted = adv_is_chip_halted(adv);
1119 adv_host_req_chip_halt(adv);
1122 adv_set_sdtr_reg_at_id(adv, tid, sdtr_data);
1129 adv->fix_asyn_xfer &= ~ADV_TID_TO_TARGET_MASK(tid);
1133 adv_start_chip(adv);
1174 adv_period_offset_to_sdtr(struct adv_softc *adv, u_int *period,
1193 for (i = 0; i < adv->sdtr_period_tbl_size; i++) {
1194 if (*period <= adv->sdtr_period_tbl[i]) {
1207 *period = adv->sdtr_period_tbl[0];
1216 if (adv->fix_asyn_xfer & ADV_TID_TO_TARGET_MASK(tid))
1224 adv_read_lram_16_multi(struct adv_softc *adv, u_int16_t s_addr,
1227 ADV_OUTW(adv, ADV_LRAM_ADDR, s_addr);
1228 ADV_INSW(adv, ADV_LRAM_DATA, buffer, count);
1232 adv_write_lram_16_multi(struct adv_softc *adv, u_int16_t s_addr,
1235 ADV_OUTW(adv, ADV_LRAM_ADDR, s_addr);
1236 ADV_OUTSW(adv, ADV_LRAM_DATA, buffer, count);
1240 adv_mset_lram_16(struct adv_softc *adv, u_int16_t s_addr,
1243 ADV_OUTW(adv, ADV_LRAM_ADDR, s_addr);
1244 bus_set_multi_2(adv->res, adv->reg_off + ADV_LRAM_DATA,
1249 adv_msum_lram_16(struct adv_softc *adv, u_int16_t s_addr, int count)
1255 ADV_OUTW(adv, ADV_LRAM_ADDR, s_addr);
1257 sum += ADV_INW(adv, ADV_LRAM_DATA);
1262 adv_write_and_verify_lram_16(struct adv_softc *adv, u_int16_t addr,
1268 ADV_OUTW(adv, ADV_LRAM_ADDR, addr);
1269 ADV_OUTW(adv, ADV_LRAM_DATA, value);
1271 ADV_OUTW(adv, ADV_LRAM_ADDR, addr);
1272 if (value != ADV_INW(adv, ADV_LRAM_DATA))
1278 adv_read_lram_32(struct adv_softc *adv, u_int16_t addr)
1282 ADV_OUTW(adv, ADV_LRAM_ADDR, addr);
1285 val_high = ADV_INW(adv, ADV_LRAM_DATA);
1286 val_low = ADV_INW(adv, ADV_LRAM_DATA);
1288 val_low = ADV_INW(adv, ADV_LRAM_DATA);
1289 val_high = ADV_INW(adv, ADV_LRAM_DATA);
1296 adv_write_lram_32(struct adv_softc *adv, u_int16_t addr, u_int32_t value)
1298 ADV_OUTW(adv, ADV_LRAM_ADDR, addr);
1301 ADV_OUTW(adv, ADV_LRAM_DATA, (u_int16_t)((value >> 16) & 0xFFFF));
1302 ADV_OUTW(adv, ADV_LRAM_DATA, (u_int16_t)(value & 0xFFFF));
1304 ADV_OUTW(adv, ADV_LRAM_DATA, (u_int16_t)(value & 0xFFFF));
1305 ADV_OUTW(adv, ADV_LRAM_DATA, (u_int16_t)((value >> 16) & 0xFFFF));
1310 adv_write_lram_32_multi(struct adv_softc *adv, u_int16_t s_addr,
1313 ADV_OUTW(adv, ADV_LRAM_ADDR, s_addr);
1314 ADV_OUTSW(adv, ADV_LRAM_DATA, (u_int16_t *)buffer, count * 2);
1318 adv_read_eeprom_16(struct adv_softc *adv, u_int8_t addr)
1323 adv_write_eeprom_cmd_reg(adv, ADV_EEPROM_CMD_WRITE_DISABLE);
1326 adv_write_eeprom_cmd_reg(adv, cmd_reg);
1328 read_wval = ADV_INW(adv, ADV_EEPROM_DATA);
1334 adv_write_eeprom_16(struct adv_softc *adv, u_int8_t addr, u_int16_t value)
1338 read_value = adv_read_eeprom_16(adv, addr);
1340 adv_write_eeprom_cmd_reg(adv, ADV_EEPROM_CMD_WRITE_ENABLE);
1343 ADV_OUTW(adv, ADV_EEPROM_DATA, value);
1346 adv_write_eeprom_cmd_reg(adv, ADV_EEPROM_CMD_WRITE | addr);
1349 adv_write_eeprom_cmd_reg(adv, ADV_EEPROM_CMD_WRITE_DISABLE);
1351 read_value = adv_read_eeprom_16(adv, addr);
1357 adv_write_eeprom_cmd_reg(struct adv_softc *adv, u_int8_t cmd_reg)
1364 ADV_OUTB(adv, ADV_EEPROM_CMD, cmd_reg);
1366 read_back = ADV_INB(adv, ADV_EEPROM_CMD);
1377 adv_set_eeprom_config_once(struct adv_softc *adv,
1392 if (*wbuf != adv_write_eeprom_16(adv, s_addr, *wbuf)) {
1396 if (adv->type & ADV_VL) {
1406 if (*wbuf != adv_write_eeprom_16(adv, s_addr, *wbuf)) {
1411 if (sum != adv_write_eeprom_16(adv, s_addr, sum)) {
1416 if (*wbuf != adv_read_eeprom_16(adv, s_addr)) {
1421 if (*wbuf != adv_read_eeprom_16(adv, s_addr)) {
1429 adv_load_microcode(struct adv_softc *adv, u_int16_t s_addr,
1438 adv_mset_lram_16(adv, s_addr, 0, mcode_lram_size);
1439 adv_write_lram_16_multi(adv, s_addr, mcode_buf, mcode_lram_size);
1441 chksum = adv_msum_lram_16(adv, s_addr, mcode_lram_size);
1442 mcode_chksum = (u_int16_t)adv_msum_lram_16(adv, ADV_CODE_SEC_BEG,
1445 adv_write_lram_16(adv, ADVV_MCODE_CHKSUM_W, mcode_chksum);
1446 adv_write_lram_16(adv, ADVV_MCODE_SIZE_W, mcode_size);
1451 adv_reinit_lram(struct adv_softc *adv) {
1452 adv_init_lram(adv);
1453 adv_init_qlink_var(adv);
1457 adv_init_lram(struct adv_softc *adv)
1462 adv_mset_lram_16(adv, ADV_QADR_BEG, 0,
1463 (((adv->max_openings + 2 + 1) * 64) >> 1));
1468 adv_write_lram_8(adv, s_addr + ADV_SCSIQ_B_FWD, i + 1);
1469 adv_write_lram_8(adv, s_addr + ADV_SCSIQ_B_BWD, adv->max_openings);
1470 adv_write_lram_8(adv, s_addr + ADV_SCSIQ_B_QNO, i);
1473 for (; i < adv->max_openings; i++, s_addr += ADV_QBLK_SIZE) {
1474 adv_write_lram_8(adv, s_addr + ADV_SCSIQ_B_FWD, i + 1);
1475 adv_write_lram_8(adv, s_addr + ADV_SCSIQ_B_BWD, i - 1);
1476 adv_write_lram_8(adv, s_addr + ADV_SCSIQ_B_QNO, i);
1479 adv_write_lram_8(adv, s_addr + ADV_SCSIQ_B_FWD, ADV_QLINK_END);
1480 adv_write_lram_8(adv, s_addr + ADV_SCSIQ_B_BWD, adv->max_openings - 1);
1481 adv_write_lram_8(adv, s_addr + ADV_SCSIQ_B_QNO, adv->max_openings);
1485 for (; i <= adv->max_openings + 3; i++, s_addr += ADV_QBLK_SIZE) {
1486 adv_write_lram_8(adv, s_addr + ADV_SCSIQ_B_FWD, i);
1487 adv_write_lram_8(adv, s_addr + ADV_SCSIQ_B_BWD, i);
1488 adv_write_lram_8(adv, s_addr + ADV_SCSIQ_B_QNO, i);
1493 adv_init_microcode_var(struct adv_softc *adv)
1500 adv_set_syncrate(adv, /*path*/NULL,
1505 adv_init_qlink_var(adv);
1507 adv_write_lram_8(adv, ADVV_DISC_ENABLE_B, adv->disc_enable);
1508 adv_write_lram_8(adv, ADVV_HOSTSCSI_ID_B, 0x01 << adv->scsi_id);
1510 adv_write_lram_32(adv, ADVV_OVERRUN_PADDR_D, adv->overrun_physbase);
1512 adv_write_lram_32(adv, ADVV_OVERRUN_BSIZE_D, ADV_OVERRUN_BSIZE);
1514 ADV_OUTW(adv, ADV_REG_PROG_COUNTER, ADV_MCODE_START_ADDR);
1515 if (ADV_INW(adv, ADV_REG_PROG_COUNTER) != ADV_MCODE_START_ADDR) {
1516 device_printf(adv->dev,
1524 adv_init_qlink_var(struct adv_softc *adv)
1529 adv_write_lram_8(adv, ADVV_NEXTRDY_B, 1);
1530 adv_write_lram_8(adv, ADVV_DONENEXT_B, adv->max_openings);
1532 adv_write_lram_16(adv, ADVV_FREE_Q_HEAD_W, 1);
1533 adv_write_lram_16(adv, ADVV_DONE_Q_TAIL_W, adv->max_openings);
1535 adv_write_lram_8(adv, ADVV_BUSY_QHEAD_B,
1536 (u_int8_t)((int) adv->max_openings + 1));
1537 adv_write_lram_8(adv, ADVV_DISC1_QHEAD_B,
1538 (u_int8_t)((int) adv->max_openings + 2));
1540 adv_write_lram_8(adv, ADVV_TOTAL_READY_Q_B, adv->max_openings);
1542 adv_write_lram_16(adv, ADVV_ASCDVC_ERR_CODE_W, 0);
1543 adv_write_lram_16(adv, ADVV_HALTCODE_W, 0);
1544 adv_write_lram_8(adv, ADVV_STOP_CODE_B, 0);
1545 adv_write_lram_8(adv, ADVV_SCSIBUSY_B, 0);
1546 adv_write_lram_8(adv, ADVV_WTM_FLAG_B, 0);
1547 adv_write_lram_8(adv, ADVV_Q_DONE_IN_PROGRESS_B, 0);
1551 adv_write_lram_16(adv, lram_addr, 0);
1555 adv_disable_interrupt(struct adv_softc *adv)
1559 cfg = ADV_INW(adv, ADV_CONFIG_LSW);
1560 ADV_OUTW(adv, ADV_CONFIG_LSW, cfg & ~ADV_CFG_LSW_HOST_INT_ON);
1564 adv_enable_interrupt(struct adv_softc *adv)
1568 cfg = ADV_INW(adv, ADV_CONFIG_LSW);
1569 ADV_OUTW(adv, ADV_CONFIG_LSW, cfg | ADV_CFG_LSW_HOST_INT_ON);
1573 adv_toggle_irq_act(struct adv_softc *adv)
1575 ADV_OUTW(adv, ADV_CHIP_STATUS, ADV_CIW_IRQ_ACT);
1576 ADV_OUTW(adv, ADV_CHIP_STATUS, 0);
1580 adv_start_execution(struct adv_softc *adv)
1582 if (adv_read_lram_8(adv, ADV_STOP_CODE_B) != 0) {
1583 adv_write_lram_8(adv, ADV_STOP_CODE_B, 0);
1588 adv_stop_chip(struct adv_softc *adv)
1592 cc_val = ADV_INB(adv, ADV_CHIP_CTRL)
1594 ADV_OUTB(adv, ADV_CHIP_CTRL, cc_val | ADV_CC_HALT);
1595 adv_set_chip_ih(adv, ADV_INS_HALT);
1596 adv_set_chip_ih(adv, ADV_INS_RFLAG_WTM);
1597 if ((ADV_INW(adv, ADV_CHIP_STATUS) & ADV_CSW_HALTED) == 0) {
1604 adv_host_req_chip_halt(struct adv_softc *adv)
1609 if (adv_is_chip_halted(adv))
1613 saved_stop_code = adv_read_lram_8(adv, ADVV_STOP_CODE_B);
1614 adv_write_lram_8(adv, ADVV_STOP_CODE_B,
1616 while (adv_is_chip_halted(adv) == 0
1620 adv_write_lram_8(adv, ADVV_STOP_CODE_B, saved_stop_code);
1625 adv_set_chip_ih(struct adv_softc *adv, u_int16_t ins_code)
1627 adv_set_bank(adv, 1);
1628 ADV_OUTW(adv, ADV_REG_IH, ins_code);
1629 adv_set_bank(adv, 0);
1634 adv_get_chip_scsi_ctrl(struct adv_softc *adv)
1638 adv_set_bank(adv, 1);
1639 scsi_ctrl = ADV_INB(adv, ADV_REG_SC);
1640 adv_set_bank(adv, 0);
1650 adv_get_q_info(struct adv_softc *adv, u_int16_t s_addr,
1655 ADV_OUTW(adv, ADV_LRAM_ADDR, s_addr);
1660 *inbuf = ADV_INW(adv, ADV_LRAM_DATA);
1665 adv_get_num_free_queues(struct adv_softc *adv, u_int8_t n_qs)
1670 cur_used_qs = adv->cur_active + ADV_MIN_FREE_Q;
1672 if ((cur_used_qs + n_qs) <= adv->max_openings) {
1673 cur_free_qs = adv->max_openings - cur_used_qs;
1676 adv->openings_needed = n_qs;
1681 adv_alloc_free_queues(struct adv_softc *adv, u_int8_t free_q_head,
1687 free_q_head = adv_alloc_free_queue(adv, free_q_head);
1695 adv_alloc_free_queue(struct adv_softc *adv, u_int8_t free_q_head)
1703 q_status = adv_read_lram_8(adv, q_addr + ADV_SCSIQ_B_STATUS);
1706 next_qp = adv_read_lram_8(adv, q_addr + ADV_SCSIQ_B_FWD);
1712 adv_send_scsi_queue(struct adv_softc *adv, struct adv_scsi_q *scsiq,
1724 free_q_head = adv_read_lram_16(adv, ADVV_FREE_Q_HEAD_W) & 0xFF;
1725 if ((next_qp = adv_alloc_free_queues(adv, free_q_head, n_q_required))
1734 scsiq->q1.sense_addr = adv->sense_physbase
1736 adv_put_ready_sg_list_queue(adv, scsiq, free_q_head);
1737 adv_write_lram_16(adv, ADVV_FREE_Q_HEAD_W, next_qp);
1738 adv->cur_active += n_q_required;
1746 adv_put_ready_sg_list_queue(struct adv_softc *adv, struct adv_scsi_q *scsiq,
1793 next_qp = adv_read_lram_8(adv, q_addr + ADV_SCSIQ_B_FWD);
1797 adv_write_lram_16_multi(adv,
1801 adv_write_lram_32_multi(adv, q_addr + ADV_SGQ_LIST_BEG,
1808 adv_put_ready_queue(adv, scsiq, q_no);
1812 adv_put_ready_queue(struct adv_softc *adv, struct adv_scsi_q *scsiq,
1820 tinfo = &adv->tinfo[tid_no];
1824 adv_msgout_sdtr(adv, tinfo->goal.period, tinfo->goal.offset);
1831 adv_write_lram_16_multi(adv, q_addr + ADV_SCSIQ_CDB_BEG,
1839 adv_put_scsiq(adv, q_addr + ADV_SCSIQ_CPY_BEG,
1844 adv_write_lram_16(adv, q_addr + ADV_SCSIQ_W_REQ_COUNT,
1845 adv->req_count);
1850 adv_write_lram_32(adv, q_addr + ADV_SCSIQ_DW_REMAIN_XFER_ADDR, 0);
1851 adv_write_lram_32(adv, q_addr + ADV_SCSIQ_DW_REMAIN_XFER_CNT, 0);
1854 adv_write_lram_16(adv, q_addr + ADV_SCSIQ_B_STATUS,
1859 adv_put_scsiq(struct adv_softc *adv, u_int16_t s_addr,
1879 ADV_OUTW(adv, ADV_LRAM_ADDR, s_addr);
1884 ADV_OUTW(adv, ADV_LRAM_DATA, *buffer);
1893 panic("adv(4) not supported on big-endian machines.\n");
1900 panic("adv(4) not supported on big-endian machines.\n");
1905 adv_handle_extmsg_in(struct adv_softc *adv, u_int16_t halt_q_addr,
1911 adv_read_lram_16_multi(adv, ADVV_MSGIN_BEG, (u_int16_t *) &ext_msg,
1925 adv_read_lram_32(adv, halt_q_addr + ADV_SCSIQ_D_CINFO_IDX);
1926 ccb = adv->ccb_infos[cinfo_index].ccb;
1927 tinfo = &adv->tinfo[tid_no];
1939 adv_period_offset_to_sdtr(adv, &period, &offset, tid_no);
1944 adv_set_syncrate(adv, ccb->ccb_h.path,
1959 adv_msgout_sdtr(adv, ext_msg.xfer_period,
1968 adv_write_lram_16_multi(adv, ADVV_MSGOUT_BEG,
1975 adv_write_lram_16_multi(adv, ADVV_MSGOUT_BEG,
1980 adv_write_lram_8(adv, halt_q_addr + ADV_SCSIQ_B_CNTL, q_cntl);
1984 adv_msgout_sdtr(struct adv_softc *adv, u_int8_t sdtr_period,
1995 adv_write_lram_16_multi(adv, ADVV_MSGOUT_BEG,
2001 adv_abort_ccb(struct adv_softc *adv, int target, int lun, union ccb *ccb,
2012 mtx_assert(&adv->lock, MA_OWNED);
2016 for (q_no = ADV_MIN_ACTIVE_QNO; q_no <= adv->max_openings; q_no++) {
2020 adv_copy_lram_doneq(adv, q_addr, scsiq, adv->max_dma_count);
2021 ccb_info = &adv->ccb_infos[scsiq->d2.ccb_index];
2033 adv_write_lram_8(adv, q_addr + ADV_SCSIQ_B_STATUS,
2050 adv_reset_bus(struct adv_softc *adv, int initiate_bus_reset)
2057 mtx_assert(&adv->lock, MA_OWNED);
2059 while ((ADV_INW(adv, ADV_CHIP_STATUS) & ADV_CSW_SCSI_RESET_ACTIVE) != 0
2062 adv_reset_chip(adv, initiate_bus_reset);
2063 adv_reinit_lram(adv);
2065 adv_set_syncrate(adv, NULL, i, /*period*/0,
2067 ADV_OUTW(adv, ADV_REG_PROG_COUNTER, ADV_MCODE_START_ADDR);
2070 if (adv->path != NULL)
2071 xpt_async(AC_BUS_RESET, adv->path, NULL);
2074 while ((ccb = (union ccb *)LIST_FIRST(&adv->pending_ccbs)) != NULL) {
2077 adv_done(adv, ccb, QD_ABORTED_BY_HOST, 0, 0, 0);
2081 adv_start_chip(adv);
2086 adv_set_sdtr_reg_at_id(struct adv_softc *adv, int tid, u_int8_t sdtr_data)
2090 adv_set_bank(adv, 1);
2091 orig_id = ffs(ADV_INB(adv, ADV_HOST_SCSIID)) - 1;
2092 ADV_OUTB(adv, ADV_HOST_SCSIID, tid);
2093 if (ADV_INB(adv, ADV_HOST_SCSIID) == (0x01 << tid)) {
2094 adv_set_bank(adv, 0);
2095 ADV_OUTB(adv, ADV_SYN_OFFSET, sdtr_data);
2097 adv_set_bank(adv, 1);
2098 ADV_OUTB(adv, ADV_HOST_SCSIID, orig_id);
2099 adv_set_bank(adv, 0);