Lines Matching refs:block_id
56 static inline uint64_t CVMX_USBNX_BIST_STATUS(unsigned long block_id)
59 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
60 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
61 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
62 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
63 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
64 cvmx_warn("CVMX_USBNX_BIST_STATUS(%lu) is invalid on this chip\n", block_id);
65 return CVMX_ADD_IO_SEG(0x00011800680007F8ull) + ((block_id) & 1) * 0x10000000ull;
68 #define CVMX_USBNX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800680007F8ull) + ((block_id) & 1) * 0x10000000ull)
71 static inline uint64_t CVMX_USBNX_CLK_CTL(unsigned long block_id)
74 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
75 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
76 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
77 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
78 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
79 cvmx_warn("CVMX_USBNX_CLK_CTL(%lu) is invalid on this chip\n", block_id);
80 return CVMX_ADD_IO_SEG(0x0001180068000010ull) + ((block_id) & 1) * 0x10000000ull;
83 #define CVMX_USBNX_CLK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180068000010ull) + ((block_id) & 1) * 0x10000000ull)
86 static inline uint64_t CVMX_USBNX_CTL_STATUS(unsigned long block_id)
89 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
90 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
91 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
92 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
93 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
94 cvmx_warn("CVMX_USBNX_CTL_STATUS(%lu) is invalid on this chip\n", block_id);
95 return CVMX_ADD_IO_SEG(0x00016F0000000800ull) + ((block_id) & 1) * 0x100000000000ull;
98 #define CVMX_USBNX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000800ull) + ((block_id) & 1) * 0x100000000000ull)
101 static inline uint64_t CVMX_USBNX_DMA0_INB_CHN0(unsigned long block_id)
104 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
105 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
106 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
107 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
108 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
109 cvmx_warn("CVMX_USBNX_DMA0_INB_CHN0(%lu) is invalid on this chip\n", block_id);
110 return CVMX_ADD_IO_SEG(0x00016F0000000818ull) + ((block_id) & 1) * 0x100000000000ull;
113 #define CVMX_USBNX_DMA0_INB_CHN0(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000818ull) + ((block_id) & 1) * 0x100000000000ull)
116 static inline uint64_t CVMX_USBNX_DMA0_INB_CHN1(unsigned long block_id)
119 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
120 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
121 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
122 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
123 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
124 cvmx_warn("CVMX_USBNX_DMA0_INB_CHN1(%lu) is invalid on this chip\n", block_id);
125 return CVMX_ADD_IO_SEG(0x00016F0000000820ull) + ((block_id) & 1) * 0x100000000000ull;
128 #define CVMX_USBNX_DMA0_INB_CHN1(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000820ull) + ((block_id) & 1) * 0x100000000000ull)
131 static inline uint64_t CVMX_USBNX_DMA0_INB_CHN2(unsigned long block_id)
134 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
135 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
136 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
137 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
138 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
139 cvmx_warn("CVMX_USBNX_DMA0_INB_CHN2(%lu) is invalid on this chip\n", block_id);
140 return CVMX_ADD_IO_SEG(0x00016F0000000828ull) + ((block_id) & 1) * 0x100000000000ull;
143 #define CVMX_USBNX_DMA0_INB_CHN2(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000828ull) + ((block_id) & 1) * 0x100000000000ull)
146 static inline uint64_t CVMX_USBNX_DMA0_INB_CHN3(unsigned long block_id)
149 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
150 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
151 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
152 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
153 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
154 cvmx_warn("CVMX_USBNX_DMA0_INB_CHN3(%lu) is invalid on this chip\n", block_id);
155 return CVMX_ADD_IO_SEG(0x00016F0000000830ull) + ((block_id) & 1) * 0x100000000000ull;
158 #define CVMX_USBNX_DMA0_INB_CHN3(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000830ull) + ((block_id) & 1) * 0x100000000000ull)
161 static inline uint64_t CVMX_USBNX_DMA0_INB_CHN4(unsigned long block_id)
164 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
165 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
166 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
167 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
168 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
169 cvmx_warn("CVMX_USBNX_DMA0_INB_CHN4(%lu) is invalid on this chip\n", block_id);
170 return CVMX_ADD_IO_SEG(0x00016F0000000838ull) + ((block_id) & 1) * 0x100000000000ull;
173 #define CVMX_USBNX_DMA0_INB_CHN4(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000838ull) + ((block_id) & 1) * 0x100000000000ull)
176 static inline uint64_t CVMX_USBNX_DMA0_INB_CHN5(unsigned long block_id)
179 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
180 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
181 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
182 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
183 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
184 cvmx_warn("CVMX_USBNX_DMA0_INB_CHN5(%lu) is invalid on this chip\n", block_id);
185 return CVMX_ADD_IO_SEG(0x00016F0000000840ull) + ((block_id) & 1) * 0x100000000000ull;
188 #define CVMX_USBNX_DMA0_INB_CHN5(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000840ull) + ((block_id) & 1) * 0x100000000000ull)
191 static inline uint64_t CVMX_USBNX_DMA0_INB_CHN6(unsigned long block_id)
194 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
195 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
196 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
197 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
198 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
199 cvmx_warn("CVMX_USBNX_DMA0_INB_CHN6(%lu) is invalid on this chip\n", block_id);
200 return CVMX_ADD_IO_SEG(0x00016F0000000848ull) + ((block_id) & 1) * 0x100000000000ull;
203 #define CVMX_USBNX_DMA0_INB_CHN6(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000848ull) + ((block_id) & 1) * 0x100000000000ull)
206 static inline uint64_t CVMX_USBNX_DMA0_INB_CHN7(unsigned long block_id)
209 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
210 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
211 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
212 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
213 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
214 cvmx_warn("CVMX_USBNX_DMA0_INB_CHN7(%lu) is invalid on this chip\n", block_id);
215 return CVMX_ADD_IO_SEG(0x00016F0000000850ull) + ((block_id) & 1) * 0x100000000000ull;
218 #define CVMX_USBNX_DMA0_INB_CHN7(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000850ull) + ((block_id) & 1) * 0x100000000000ull)
221 static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN0(unsigned long block_id)
224 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
225 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
226 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
227 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
228 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
229 cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN0(%lu) is invalid on this chip\n", block_id);
230 return CVMX_ADD_IO_SEG(0x00016F0000000858ull) + ((block_id) & 1) * 0x100000000000ull;
233 #define CVMX_USBNX_DMA0_OUTB_CHN0(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000858ull) + ((block_id) & 1) * 0x100000000000ull)
236 static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN1(unsigned long block_id)
239 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
240 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
241 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
242 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
243 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
244 cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN1(%lu) is invalid on this chip\n", block_id);
245 return CVMX_ADD_IO_SEG(0x00016F0000000860ull) + ((block_id) & 1) * 0x100000000000ull;
248 #define CVMX_USBNX_DMA0_OUTB_CHN1(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000860ull) + ((block_id) & 1) * 0x100000000000ull)
251 static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN2(unsigned long block_id)
254 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
255 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
256 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
257 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
258 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
259 cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN2(%lu) is invalid on this chip\n", block_id);
260 return CVMX_ADD_IO_SEG(0x00016F0000000868ull) + ((block_id) & 1) * 0x100000000000ull;
263 #define CVMX_USBNX_DMA0_OUTB_CHN2(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000868ull) + ((block_id) & 1) * 0x100000000000ull)
266 static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN3(unsigned long block_id)
269 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
270 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
271 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
272 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
273 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
274 cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN3(%lu) is invalid on this chip\n", block_id);
275 return CVMX_ADD_IO_SEG(0x00016F0000000870ull) + ((block_id) & 1) * 0x100000000000ull;
278 #define CVMX_USBNX_DMA0_OUTB_CHN3(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000870ull) + ((block_id) & 1) * 0x100000000000ull)
281 static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN4(unsigned long block_id)
284 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
285 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
286 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
287 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
288 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
289 cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN4(%lu) is invalid on this chip\n", block_id);
290 return CVMX_ADD_IO_SEG(0x00016F0000000878ull) + ((block_id) & 1) * 0x100000000000ull;
293 #define CVMX_USBNX_DMA0_OUTB_CHN4(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000878ull) + ((block_id) & 1) * 0x100000000000ull)
296 static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN5(unsigned long block_id)
299 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
300 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
301 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
302 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
303 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
304 cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN5(%lu) is invalid on this chip\n", block_id);
305 return CVMX_ADD_IO_SEG(0x00016F0000000880ull) + ((block_id) & 1) * 0x100000000000ull;
308 #define CVMX_USBNX_DMA0_OUTB_CHN5(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000880ull) + ((block_id) & 1) * 0x100000000000ull)
311 static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN6(unsigned long block_id)
314 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
315 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
316 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
317 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
318 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
319 cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN6(%lu) is invalid on this chip\n", block_id);
320 return CVMX_ADD_IO_SEG(0x00016F0000000888ull) + ((block_id) & 1) * 0x100000000000ull;
323 #define CVMX_USBNX_DMA0_OUTB_CHN6(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000888ull) + ((block_id) & 1) * 0x100000000000ull)
326 static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN7(unsigned long block_id)
329 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
330 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
331 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
332 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
333 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
334 cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN7(%lu) is invalid on this chip\n", block_id);
335 return CVMX_ADD_IO_SEG(0x00016F0000000890ull) + ((block_id) & 1) * 0x100000000000ull;
338 #define CVMX_USBNX_DMA0_OUTB_CHN7(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000890ull) + ((block_id) & 1) * 0x100000000000ull)
341 static inline uint64_t CVMX_USBNX_DMA_TEST(unsigned long block_id)
344 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
345 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
346 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
347 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
348 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
349 cvmx_warn("CVMX_USBNX_DMA_TEST(%lu) is invalid on this chip\n", block_id);
350 return CVMX_ADD_IO_SEG(0x00016F0000000808ull) + ((block_id) & 1) * 0x100000000000ull;
353 #define CVMX_USBNX_DMA_TEST(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000808ull) + ((block_id) & 1) * 0x100000000000ull)
356 static inline uint64_t CVMX_USBNX_INT_ENB(unsigned long block_id)
359 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
360 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
361 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
362 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
363 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
364 cvmx_warn("CVMX_USBNX_INT_ENB(%lu) is invalid on this chip\n", block_id);
365 return CVMX_ADD_IO_SEG(0x0001180068000008ull) + ((block_id) & 1) * 0x10000000ull;
368 #define CVMX_USBNX_INT_ENB(block_id) (CVMX_ADD_IO_SEG(0x0001180068000008ull) + ((block_id) & 1) * 0x10000000ull)
371 static inline uint64_t CVMX_USBNX_INT_SUM(unsigned long block_id)
374 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
375 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
376 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
377 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
378 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
379 cvmx_warn("CVMX_USBNX_INT_SUM(%lu) is invalid on this chip\n", block_id);
380 return CVMX_ADD_IO_SEG(0x0001180068000000ull) + ((block_id) & 1) * 0x10000000ull;
383 #define CVMX_USBNX_INT_SUM(block_id) (CVMX_ADD_IO_SEG(0x0001180068000000ull) + ((block_id) & 1) * 0x10000000ull)
386 static inline uint64_t CVMX_USBNX_USBP_CTL_STATUS(unsigned long block_id)
389 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
390 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
391 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
392 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
393 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0)))))
394 cvmx_warn("CVMX_USBNX_USBP_CTL_STATUS(%lu) is invalid on this chip\n", block_id);
395 return CVMX_ADD_IO_SEG(0x0001180068000018ull) + ((block_id) & 1) * 0x10000000ull;
398 #define CVMX_USBNX_USBP_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x0001180068000018ull) + ((block_id) & 1) * 0x10000000ull)