contrib/octeon-sdk/cvmx-nand.c

187 #define ULL unsigned long long
699                 uint64_t nand_size_bits = (64*1024*1024ULL) << ((nand_id_buffer[4] & 0x70) >> 4); /* Plane size */
710                 cvmx_nand_state[chip].blocks = nand_size_bits/(8ULL*cvmx_nand_state[chip].page_size*cvmx_nand_state[chip].pages_per_block);
864     CVMX_NAND_LOG_PARAM("0x%llx", (ULL)cmd.u64[0]);
865     CVMX_NAND_LOG_PARAM("0x%llx", (ULL)cmd.u64[1]);
1136     CVMX_NAND_LOG_PARAM("0x%llx", (ULL)buffer_address);
1210     CVMX_NAND_LOG_PARAM("0x%llx", (ULL)nand_address);
1212     CVMX_NAND_LOG_PARAM("0x%llx", (ULL)buffer_address);
1300     CVMX_NAND_LOG_PARAM("0x%llx", (ULL)nand_address);
1301     CVMX_NAND_LOG_PARAM("0x%llx", (ULL)buffer_address);
1348     CVMX_NAND_LOG_PARAM("0x%llx", (ULL)nand_address);
1349     CVMX_NAND_LOG_PARAM("0x%llx", (ULL)buffer_address);
1429     CVMX_NAND_LOG_PARAM("0x%llx", (ULL)nand_address);
1493     CVMX_NAND_LOG_PARAM("0x%llx", (ULL)nand_address);
1494     CVMX_NAND_LOG_PARAM("0x%llx", (ULL)buffer_address);
1534     CVMX_NAND_LOG_PARAM("0x%llx", (ULL)buffer_address);