Lines Matching refs:block_id
56 static inline uint64_t CVMX_LMCX_BIST_CTL(unsigned long block_id)
59 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
60 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
61 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
62 cvmx_warn("CVMX_LMCX_BIST_CTL(%lu) is invalid on this chip\n", block_id);
63 return CVMX_ADD_IO_SEG(0x00011800880000F0ull) + ((block_id) & 1) * 0x60000000ull;
66 #define CVMX_LMCX_BIST_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000F0ull) + ((block_id) & 1) * 0x60000000ull)
69 static inline uint64_t CVMX_LMCX_BIST_RESULT(unsigned long block_id)
72 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
73 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
74 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
75 cvmx_warn("CVMX_LMCX_BIST_RESULT(%lu) is invalid on this chip\n", block_id);
76 return CVMX_ADD_IO_SEG(0x00011800880000F8ull) + ((block_id) & 1) * 0x60000000ull;
79 #define CVMX_LMCX_BIST_RESULT(block_id) (CVMX_ADD_IO_SEG(0x00011800880000F8ull) + ((block_id) & 1) * 0x60000000ull)
82 static inline uint64_t CVMX_LMCX_CHAR_CTL(unsigned long block_id)
85 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
86 cvmx_warn("CVMX_LMCX_CHAR_CTL(%lu) is invalid on this chip\n", block_id);
90 #define CVMX_LMCX_CHAR_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000220ull))
93 static inline uint64_t CVMX_LMCX_CHAR_MASK0(unsigned long block_id)
96 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
97 cvmx_warn("CVMX_LMCX_CHAR_MASK0(%lu) is invalid on this chip\n", block_id);
101 #define CVMX_LMCX_CHAR_MASK0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000228ull))
104 static inline uint64_t CVMX_LMCX_CHAR_MASK1(unsigned long block_id)
107 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
108 cvmx_warn("CVMX_LMCX_CHAR_MASK1(%lu) is invalid on this chip\n", block_id);
112 #define CVMX_LMCX_CHAR_MASK1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000230ull))
115 static inline uint64_t CVMX_LMCX_CHAR_MASK2(unsigned long block_id)
118 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
119 cvmx_warn("CVMX_LMCX_CHAR_MASK2(%lu) is invalid on this chip\n", block_id);
123 #define CVMX_LMCX_CHAR_MASK2(block_id) (CVMX_ADD_IO_SEG(0x0001180088000238ull))
126 static inline uint64_t CVMX_LMCX_CHAR_MASK3(unsigned long block_id)
129 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
130 cvmx_warn("CVMX_LMCX_CHAR_MASK3(%lu) is invalid on this chip\n", block_id);
134 #define CVMX_LMCX_CHAR_MASK3(block_id) (CVMX_ADD_IO_SEG(0x0001180088000240ull))
137 static inline uint64_t CVMX_LMCX_CHAR_MASK4(unsigned long block_id)
140 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
141 cvmx_warn("CVMX_LMCX_CHAR_MASK4(%lu) is invalid on this chip\n", block_id);
145 #define CVMX_LMCX_CHAR_MASK4(block_id) (CVMX_ADD_IO_SEG(0x0001180088000318ull))
148 static inline uint64_t CVMX_LMCX_COMP_CTL(unsigned long block_id)
151 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
152 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
153 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
154 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
155 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
156 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
157 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0)))))
158 cvmx_warn("CVMX_LMCX_COMP_CTL(%lu) is invalid on this chip\n", block_id);
159 return CVMX_ADD_IO_SEG(0x0001180088000028ull) + ((block_id) & 1) * 0x60000000ull;
162 #define CVMX_LMCX_COMP_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000028ull) + ((block_id) & 1) * 0x60000000ull)
165 static inline uint64_t CVMX_LMCX_COMP_CTL2(unsigned long block_id)
168 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
169 cvmx_warn("CVMX_LMCX_COMP_CTL2(%lu) is invalid on this chip\n", block_id);
173 #define CVMX_LMCX_COMP_CTL2(block_id) (CVMX_ADD_IO_SEG(0x00011800880001B8ull))
176 static inline uint64_t CVMX_LMCX_CONFIG(unsigned long block_id)
179 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
180 cvmx_warn("CVMX_LMCX_CONFIG(%lu) is invalid on this chip\n", block_id);
184 #define CVMX_LMCX_CONFIG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000188ull))
187 static inline uint64_t CVMX_LMCX_CONTROL(unsigned long block_id)
190 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
191 cvmx_warn("CVMX_LMCX_CONTROL(%lu) is invalid on this chip\n", block_id);
195 #define CVMX_LMCX_CONTROL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000190ull))
198 static inline uint64_t CVMX_LMCX_CTL(unsigned long block_id)
201 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
202 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
203 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
204 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
205 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
206 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
207 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0)))))
208 cvmx_warn("CVMX_LMCX_CTL(%lu) is invalid on this chip\n", block_id);
209 return CVMX_ADD_IO_SEG(0x0001180088000010ull) + ((block_id) & 1) * 0x60000000ull;
212 #define CVMX_LMCX_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000010ull) + ((block_id) & 1) * 0x60000000ull)
215 static inline uint64_t CVMX_LMCX_CTL1(unsigned long block_id)
218 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
219 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
220 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
221 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
222 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0)))))
223 cvmx_warn("CVMX_LMCX_CTL1(%lu) is invalid on this chip\n", block_id);
224 return CVMX_ADD_IO_SEG(0x0001180088000090ull) + ((block_id) & 1) * 0x60000000ull;
227 #define CVMX_LMCX_CTL1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000090ull) + ((block_id) & 1) * 0x60000000ull)
230 static inline uint64_t CVMX_LMCX_DCLK_CNT(unsigned long block_id)
233 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
234 cvmx_warn("CVMX_LMCX_DCLK_CNT(%lu) is invalid on this chip\n", block_id);
238 #define CVMX_LMCX_DCLK_CNT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001E0ull))
241 static inline uint64_t CVMX_LMCX_DCLK_CNT_HI(unsigned long block_id)
244 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
245 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
246 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
247 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
248 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
249 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
250 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0)))))
251 cvmx_warn("CVMX_LMCX_DCLK_CNT_HI(%lu) is invalid on this chip\n", block_id);
252 return CVMX_ADD_IO_SEG(0x0001180088000070ull) + ((block_id) & 1) * 0x60000000ull;
255 #define CVMX_LMCX_DCLK_CNT_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180088000070ull) + ((block_id) & 1) * 0x60000000ull)
258 static inline uint64_t CVMX_LMCX_DCLK_CNT_LO(unsigned long block_id)
261 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
262 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
263 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
264 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
265 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
266 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
267 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0)))))
268 cvmx_warn("CVMX_LMCX_DCLK_CNT_LO(%lu) is invalid on this chip\n", block_id);
269 return CVMX_ADD_IO_SEG(0x0001180088000068ull) + ((block_id) & 1) * 0x60000000ull;
272 #define CVMX_LMCX_DCLK_CNT_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180088000068ull) + ((block_id) & 1) * 0x60000000ull)
275 static inline uint64_t CVMX_LMCX_DCLK_CTL(unsigned long block_id)
278 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
279 cvmx_warn("CVMX_LMCX_DCLK_CTL(%lu) is invalid on this chip\n", block_id);
280 return CVMX_ADD_IO_SEG(0x00011800880000B8ull) + ((block_id) & 1) * 0x60000000ull;
283 #define CVMX_LMCX_DCLK_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000B8ull) + ((block_id) & 1) * 0x60000000ull)
286 static inline uint64_t CVMX_LMCX_DDR2_CTL(unsigned long block_id)
289 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
290 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
291 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
292 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
293 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
294 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
295 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0)))))
296 cvmx_warn("CVMX_LMCX_DDR2_CTL(%lu) is invalid on this chip\n", block_id);
297 return CVMX_ADD_IO_SEG(0x0001180088000018ull) + ((block_id) & 1) * 0x60000000ull;
300 #define CVMX_LMCX_DDR2_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000018ull) + ((block_id) & 1) * 0x60000000ull)
303 static inline uint64_t CVMX_LMCX_DDR_PLL_CTL(unsigned long block_id)
306 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
307 cvmx_warn("CVMX_LMCX_DDR_PLL_CTL(%lu) is invalid on this chip\n", block_id);
311 #define CVMX_LMCX_DDR_PLL_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000258ull))
314 static inline uint64_t CVMX_LMCX_DELAY_CFG(unsigned long block_id)
317 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
318 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
319 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
320 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
321 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
322 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0)))))
323 cvmx_warn("CVMX_LMCX_DELAY_CFG(%lu) is invalid on this chip\n", block_id);
324 return CVMX_ADD_IO_SEG(0x0001180088000088ull) + ((block_id) & 1) * 0x60000000ull;
327 #define CVMX_LMCX_DELAY_CFG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000088ull) + ((block_id) & 1) * 0x60000000ull)
330 static inline uint64_t CVMX_LMCX_DIMMX_PARAMS(unsigned long offset, unsigned long block_id)
333 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id == 0))))))
334 cvmx_warn("CVMX_LMCX_DIMMX_PARAMS(%lu,%lu) is invalid on this chip\n", offset, block_id);
335 return CVMX_ADD_IO_SEG(0x0001180088000270ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8;
338 #define CVMX_LMCX_DIMMX_PARAMS(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180088000270ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8)
341 static inline uint64_t CVMX_LMCX_DIMM_CTL(unsigned long block_id)
344 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
345 cvmx_warn("CVMX_LMCX_DIMM_CTL(%lu) is invalid on this chip\n", block_id);
349 #define CVMX_LMCX_DIMM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000310ull))
352 static inline uint64_t CVMX_LMCX_DLL_CTL(unsigned long block_id)
355 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
356 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
357 cvmx_warn("CVMX_LMCX_DLL_CTL(%lu) is invalid on this chip\n", block_id);
358 return CVMX_ADD_IO_SEG(0x00011800880000C0ull) + ((block_id) & 1) * 0x60000000ull;
361 #define CVMX_LMCX_DLL_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000C0ull) + ((block_id) & 1) * 0x60000000ull)
364 static inline uint64_t CVMX_LMCX_DLL_CTL2(unsigned long block_id)
367 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
368 cvmx_warn("CVMX_LMCX_DLL_CTL2(%lu) is invalid on this chip\n", block_id);
372 #define CVMX_LMCX_DLL_CTL2(block_id) (CVMX_ADD_IO_SEG(0x00011800880001C8ull))
375 static inline uint64_t CVMX_LMCX_DLL_CTL3(unsigned long block_id)
378 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
379 cvmx_warn("CVMX_LMCX_DLL_CTL3(%lu) is invalid on this chip\n", block_id);
383 #define CVMX_LMCX_DLL_CTL3(block_id) (CVMX_ADD_IO_SEG(0x0001180088000218ull))
386 static inline uint64_t CVMX_LMCX_DUAL_MEMCFG(unsigned long block_id)
389 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
390 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
391 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
392 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
393 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
394 cvmx_warn("CVMX_LMCX_DUAL_MEMCFG(%lu) is invalid on this chip\n", block_id);
395 return CVMX_ADD_IO_SEG(0x0001180088000098ull) + ((block_id) & 1) * 0x60000000ull;
398 #define CVMX_LMCX_DUAL_MEMCFG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000098ull) + ((block_id) & 1) * 0x60000000ull)
401 static inline uint64_t CVMX_LMCX_ECC_SYND(unsigned long block_id)
404 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
405 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
406 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
407 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
408 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
409 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
410 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
411 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
412 cvmx_warn("CVMX_LMCX_ECC_SYND(%lu) is invalid on this chip\n", block_id);
413 return CVMX_ADD_IO_SEG(0x0001180088000038ull) + ((block_id) & 1) * 0x60000000ull;
416 #define CVMX_LMCX_ECC_SYND(block_id) (CVMX_ADD_IO_SEG(0x0001180088000038ull) + ((block_id) & 1) * 0x60000000ull)
419 static inline uint64_t CVMX_LMCX_FADR(unsigned long block_id)
422 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
423 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
424 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
425 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
426 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
427 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
428 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
429 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
430 cvmx_warn("CVMX_LMCX_FADR(%lu) is invalid on this chip\n", block_id);
431 return CVMX_ADD_IO_SEG(0x0001180088000020ull) + ((block_id) & 1) * 0x60000000ull;
434 #define CVMX_LMCX_FADR(block_id) (CVMX_ADD_IO_SEG(0x0001180088000020ull) + ((block_id) & 1) * 0x60000000ull)
437 static inline uint64_t CVMX_LMCX_IFB_CNT(unsigned long block_id)
440 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
441 cvmx_warn("CVMX_LMCX_IFB_CNT(%lu) is invalid on this chip\n", block_id);
445 #define CVMX_LMCX_IFB_CNT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001D0ull))
448 static inline uint64_t CVMX_LMCX_IFB_CNT_HI(unsigned long block_id)
451 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
452 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
453 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
454 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
455 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
456 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
457 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0)))))
458 cvmx_warn("CVMX_LMCX_IFB_CNT_HI(%lu) is invalid on this chip\n", block_id);
459 return CVMX_ADD_IO_SEG(0x0001180088000050ull) + ((block_id) & 1) * 0x60000000ull;
462 #define CVMX_LMCX_IFB_CNT_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180088000050ull) + ((block_id) & 1) * 0x60000000ull)
465 static inline uint64_t CVMX_LMCX_IFB_CNT_LO(unsigned long block_id)
468 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
469 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
470 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
471 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
472 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
473 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
474 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0)))))
475 cvmx_warn("CVMX_LMCX_IFB_CNT_LO(%lu) is invalid on this chip\n", block_id);
476 return CVMX_ADD_IO_SEG(0x0001180088000048ull) + ((block_id) & 1) * 0x60000000ull;
479 #define CVMX_LMCX_IFB_CNT_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180088000048ull) + ((block_id) & 1) * 0x60000000ull)
482 static inline uint64_t CVMX_LMCX_INT(unsigned long block_id)
485 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
486 cvmx_warn("CVMX_LMCX_INT(%lu) is invalid on this chip\n", block_id);
490 #define CVMX_LMCX_INT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001F0ull))
493 static inline uint64_t CVMX_LMCX_INT_EN(unsigned long block_id)
496 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
497 cvmx_warn("CVMX_LMCX_INT_EN(%lu) is invalid on this chip\n", block_id);
501 #define CVMX_LMCX_INT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800880001E8ull))
504 static inline uint64_t CVMX_LMCX_MEM_CFG0(unsigned long block_id)
507 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
508 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
509 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
510 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
511 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
512 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
513 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0)))))
514 cvmx_warn("CVMX_LMCX_MEM_CFG0(%lu) is invalid on this chip\n", block_id);
515 return CVMX_ADD_IO_SEG(0x0001180088000000ull) + ((block_id) & 1) * 0x60000000ull;
518 #define CVMX_LMCX_MEM_CFG0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000000ull) + ((block_id) & 1) * 0x60000000ull)
521 static inline uint64_t CVMX_LMCX_MEM_CFG1(unsigned long block_id)
524 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
525 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
526 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
527 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
528 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
529 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
530 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0)))))
531 cvmx_warn("CVMX_LMCX_MEM_CFG1(%lu) is invalid on this chip\n", block_id);
532 return CVMX_ADD_IO_SEG(0x0001180088000008ull) + ((block_id) & 1) * 0x60000000ull;
535 #define CVMX_LMCX_MEM_CFG1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000008ull) + ((block_id) & 1) * 0x60000000ull)
538 static inline uint64_t CVMX_LMCX_MODEREG_PARAMS0(unsigned long block_id)
541 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
542 cvmx_warn("CVMX_LMCX_MODEREG_PARAMS0(%lu) is invalid on this chip\n", block_id);
546 #define CVMX_LMCX_MODEREG_PARAMS0(block_id) (CVMX_ADD_IO_SEG(0x00011800880001A8ull))
549 static inline uint64_t CVMX_LMCX_MODEREG_PARAMS1(unsigned long block_id)
552 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
553 cvmx_warn("CVMX_LMCX_MODEREG_PARAMS1(%lu) is invalid on this chip\n", block_id);
557 #define CVMX_LMCX_MODEREG_PARAMS1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000260ull))
560 static inline uint64_t CVMX_LMCX_NXM(unsigned long block_id)
563 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
564 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
565 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
566 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
567 cvmx_warn("CVMX_LMCX_NXM(%lu) is invalid on this chip\n", block_id);
568 return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + ((block_id) & 1) * 0x60000000ull;
571 #define CVMX_LMCX_NXM(block_id) (CVMX_ADD_IO_SEG(0x00011800880000C8ull) + ((block_id) & 1) * 0x60000000ull)
574 static inline uint64_t CVMX_LMCX_OPS_CNT(unsigned long block_id)
577 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
578 cvmx_warn("CVMX_LMCX_OPS_CNT(%lu) is invalid on this chip\n", block_id);
582 #define CVMX_LMCX_OPS_CNT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001D8ull))
585 static inline uint64_t CVMX_LMCX_OPS_CNT_HI(unsigned long block_id)
588 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
589 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
590 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
591 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
592 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
593 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
594 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0)))))
595 cvmx_warn("CVMX_LMCX_OPS_CNT_HI(%lu) is invalid on this chip\n", block_id);
596 return CVMX_ADD_IO_SEG(0x0001180088000060ull) + ((block_id) & 1) * 0x60000000ull;
599 #define CVMX_LMCX_OPS_CNT_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180088000060ull) + ((block_id) & 1) * 0x60000000ull)
602 static inline uint64_t CVMX_LMCX_OPS_CNT_LO(unsigned long block_id)
605 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
606 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
607 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
608 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
609 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
610 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
611 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0)))))
612 cvmx_warn("CVMX_LMCX_OPS_CNT_LO(%lu) is invalid on this chip\n", block_id);
613 return CVMX_ADD_IO_SEG(0x0001180088000058ull) + ((block_id) & 1) * 0x60000000ull;
616 #define CVMX_LMCX_OPS_CNT_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180088000058ull) + ((block_id) & 1) * 0x60000000ull)
619 static inline uint64_t CVMX_LMCX_PHY_CTL(unsigned long block_id)
622 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
623 cvmx_warn("CVMX_LMCX_PHY_CTL(%lu) is invalid on this chip\n", block_id);
627 #define CVMX_LMCX_PHY_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000210ull))
630 static inline uint64_t CVMX_LMCX_PLL_BWCTL(unsigned long block_id)
633 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
634 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
635 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0)))))
636 cvmx_warn("CVMX_LMCX_PLL_BWCTL(%lu) is invalid on this chip\n", block_id);
640 #define CVMX_LMCX_PLL_BWCTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000040ull))
643 static inline uint64_t CVMX_LMCX_PLL_CTL(unsigned long block_id)
646 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
647 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
648 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
649 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0)))))
650 cvmx_warn("CVMX_LMCX_PLL_CTL(%lu) is invalid on this chip\n", block_id);
651 return CVMX_ADD_IO_SEG(0x00011800880000A8ull) + ((block_id) & 1) * 0x60000000ull;
654 #define CVMX_LMCX_PLL_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000A8ull) + ((block_id) & 1) * 0x60000000ull)
657 static inline uint64_t CVMX_LMCX_PLL_STATUS(unsigned long block_id)
660 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
661 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
662 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
663 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0)))))
664 cvmx_warn("CVMX_LMCX_PLL_STATUS(%lu) is invalid on this chip\n", block_id);
665 return CVMX_ADD_IO_SEG(0x00011800880000B0ull) + ((block_id) & 1) * 0x60000000ull;
668 #define CVMX_LMCX_PLL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800880000B0ull) + ((block_id) & 1) * 0x60000000ull)
671 static inline uint64_t CVMX_LMCX_READ_LEVEL_CTL(unsigned long block_id)
674 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
675 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
676 cvmx_warn("CVMX_LMCX_READ_LEVEL_CTL(%lu) is invalid on this chip\n", block_id);
677 return CVMX_ADD_IO_SEG(0x0001180088000140ull) + ((block_id) & 1) * 0x60000000ull;
680 #define CVMX_LMCX_READ_LEVEL_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000140ull) + ((block_id) & 1) * 0x60000000ull)
683 static inline uint64_t CVMX_LMCX_READ_LEVEL_DBG(unsigned long block_id)
686 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
687 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
688 cvmx_warn("CVMX_LMCX_READ_LEVEL_DBG(%lu) is invalid on this chip\n", block_id);
689 return CVMX_ADD_IO_SEG(0x0001180088000148ull) + ((block_id) & 1) * 0x60000000ull;
692 #define CVMX_LMCX_READ_LEVEL_DBG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000148ull) + ((block_id) & 1) * 0x60000000ull)
695 static inline uint64_t CVMX_LMCX_READ_LEVEL_RANKX(unsigned long offset, unsigned long block_id)
698 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
699 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1))))))
700 cvmx_warn("CVMX_LMCX_READ_LEVEL_RANKX(%lu,%lu) is invalid on this chip\n", offset, block_id);
701 return CVMX_ADD_IO_SEG(0x0001180088000100ull) + (((offset) & 3) + ((block_id) & 1) * 0xC000000ull) * 8;
704 #define CVMX_LMCX_READ_LEVEL_RANKX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180088000100ull) + (((offset) & 3) + ((block_id) & 1) * 0xC000000ull) * 8)
707 static inline uint64_t CVMX_LMCX_RESET_CTL(unsigned long block_id)
710 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
711 cvmx_warn("CVMX_LMCX_RESET_CTL(%lu) is invalid on this chip\n", block_id);
715 #define CVMX_LMCX_RESET_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000180ull))
718 static inline uint64_t CVMX_LMCX_RLEVEL_CTL(unsigned long block_id)
721 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
722 cvmx_warn("CVMX_LMCX_RLEVEL_CTL(%lu) is invalid on this chip\n", block_id);
726 #define CVMX_LMCX_RLEVEL_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880002A0ull))
729 static inline uint64_t CVMX_LMCX_RLEVEL_DBG(unsigned long block_id)
732 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
733 cvmx_warn("CVMX_LMCX_RLEVEL_DBG(%lu) is invalid on this chip\n", block_id);
737 #define CVMX_LMCX_RLEVEL_DBG(block_id) (CVMX_ADD_IO_SEG(0x00011800880002A8ull))
740 static inline uint64_t CVMX_LMCX_RLEVEL_RANKX(unsigned long offset, unsigned long block_id)
743 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
744 cvmx_warn("CVMX_LMCX_RLEVEL_RANKX(%lu,%lu) is invalid on this chip\n", offset, block_id);
745 return CVMX_ADD_IO_SEG(0x0001180088000280ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 8;
748 #define CVMX_LMCX_RLEVEL_RANKX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180088000280ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 8)
751 static inline uint64_t CVMX_LMCX_RODT_COMP_CTL(unsigned long block_id)
754 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
755 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
756 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
757 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0)))))
758 cvmx_warn("CVMX_LMCX_RODT_COMP_CTL(%lu) is invalid on this chip\n", block_id);
759 return CVMX_ADD_IO_SEG(0x00011800880000A0ull) + ((block_id) & 1) * 0x60000000ull;
762 #define CVMX_LMCX_RODT_COMP_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000A0ull) + ((block_id) & 1) * 0x60000000ull)
765 static inline uint64_t CVMX_LMCX_RODT_CTL(unsigned long block_id)
768 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
769 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
770 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
771 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
772 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
773 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
774 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0)))))
775 cvmx_warn("CVMX_LMCX_RODT_CTL(%lu) is invalid on this chip\n", block_id);
776 return CVMX_ADD_IO_SEG(0x0001180088000078ull) + ((block_id) & 1) * 0x60000000ull;
779 #define CVMX_LMCX_RODT_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000078ull) + ((block_id) & 1) * 0x60000000ull)
782 static inline uint64_t CVMX_LMCX_RODT_MASK(unsigned long block_id)
785 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
786 cvmx_warn("CVMX_LMCX_RODT_MASK(%lu) is invalid on this chip\n", block_id);
790 #define CVMX_LMCX_RODT_MASK(block_id) (CVMX_ADD_IO_SEG(0x0001180088000268ull))
793 static inline uint64_t CVMX_LMCX_SLOT_CTL0(unsigned long block_id)
796 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
797 cvmx_warn("CVMX_LMCX_SLOT_CTL0(%lu) is invalid on this chip\n", block_id);
801 #define CVMX_LMCX_SLOT_CTL0(block_id) (CVMX_ADD_IO_SEG(0x00011800880001F8ull))
804 static inline uint64_t CVMX_LMCX_SLOT_CTL1(unsigned long block_id)
807 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
808 cvmx_warn("CVMX_LMCX_SLOT_CTL1(%lu) is invalid on this chip\n", block_id);
812 #define CVMX_LMCX_SLOT_CTL1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000200ull))
815 static inline uint64_t CVMX_LMCX_SLOT_CTL2(unsigned long block_id)
818 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
819 cvmx_warn("CVMX_LMCX_SLOT_CTL2(%lu) is invalid on this chip\n", block_id);
823 #define CVMX_LMCX_SLOT_CTL2(block_id) (CVMX_ADD_IO_SEG(0x0001180088000208ull))
826 static inline uint64_t CVMX_LMCX_TIMING_PARAMS0(unsigned long block_id)
829 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
830 cvmx_warn("CVMX_LMCX_TIMING_PARAMS0(%lu) is invalid on this chip\n", block_id);
834 #define CVMX_LMCX_TIMING_PARAMS0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000198ull))
837 static inline uint64_t CVMX_LMCX_TIMING_PARAMS1(unsigned long block_id)
840 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
841 cvmx_warn("CVMX_LMCX_TIMING_PARAMS1(%lu) is invalid on this chip\n", block_id);
845 #define CVMX_LMCX_TIMING_PARAMS1(block_id) (CVMX_ADD_IO_SEG(0x00011800880001A0ull))
848 static inline uint64_t CVMX_LMCX_TRO_CTL(unsigned long block_id)
851 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
852 cvmx_warn("CVMX_LMCX_TRO_CTL(%lu) is invalid on this chip\n", block_id);
856 #define CVMX_LMCX_TRO_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000248ull))
859 static inline uint64_t CVMX_LMCX_TRO_STAT(unsigned long block_id)
862 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
863 cvmx_warn("CVMX_LMCX_TRO_STAT(%lu) is invalid on this chip\n", block_id);
867 #define CVMX_LMCX_TRO_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180088000250ull))
870 static inline uint64_t CVMX_LMCX_WLEVEL_CTL(unsigned long block_id)
873 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
874 cvmx_warn("CVMX_LMCX_WLEVEL_CTL(%lu) is invalid on this chip\n", block_id);
878 #define CVMX_LMCX_WLEVEL_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000300ull))
881 static inline uint64_t CVMX_LMCX_WLEVEL_DBG(unsigned long block_id)
884 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
885 cvmx_warn("CVMX_LMCX_WLEVEL_DBG(%lu) is invalid on this chip\n", block_id);
889 #define CVMX_LMCX_WLEVEL_DBG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000308ull))
892 static inline uint64_t CVMX_LMCX_WLEVEL_RANKX(unsigned long offset, unsigned long block_id)
895 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
896 cvmx_warn("CVMX_LMCX_WLEVEL_RANKX(%lu,%lu) is invalid on this chip\n", offset, block_id);
897 return CVMX_ADD_IO_SEG(0x00011800880002B0ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 8;
900 #define CVMX_LMCX_WLEVEL_RANKX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800880002B0ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 8)
903 static inline uint64_t CVMX_LMCX_WODT_CTL0(unsigned long block_id)
906 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
907 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
908 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
909 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
910 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
911 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
912 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0)))))
913 cvmx_warn("CVMX_LMCX_WODT_CTL0(%lu) is invalid on this chip\n", block_id);
914 return CVMX_ADD_IO_SEG(0x0001180088000030ull) + ((block_id) & 1) * 0x60000000ull;
917 #define CVMX_LMCX_WODT_CTL0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000030ull) + ((block_id) & 1) * 0x60000000ull)
920 static inline uint64_t CVMX_LMCX_WODT_CTL1(unsigned long block_id)
923 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
924 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
925 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
926 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
927 cvmx_warn("CVMX_LMCX_WODT_CTL1(%lu) is invalid on this chip\n", block_id);
928 return CVMX_ADD_IO_SEG(0x0001180088000080ull) + ((block_id) & 1) * 0x60000000ull;
931 #define CVMX_LMCX_WODT_CTL1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000080ull) + ((block_id) & 1) * 0x60000000ull)
934 static inline uint64_t CVMX_LMCX_WODT_MASK(unsigned long block_id)
937 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
938 cvmx_warn("CVMX_LMCX_WODT_MASK(%lu) is invalid on this chip\n", block_id);
942 #define CVMX_LMCX_WODT_MASK(block_id) (CVMX_ADD_IO_SEG(0x00011800880001B0ull))