Lines Matching defs:write_4
97 write_4(struct macb_softc *sc, bus_size_t off, uint32_t val)
573 write_4(sc, EMAC_NCFGR, config);
576 write_4(sc, EMAC_RBQP, sc->ring_paddr_rx);
577 write_4(sc, EMAC_TBQP, sc->ring_paddr_tx);
580 write_4(sc, EMAC_NCR, RX_ENABLE | TX_ENABLE | MPE_ENABLE);
584 write_4(sc, EMAC_IER, (RCOMP_INTERRUPT |
625 write_4(sc, EMAC_TSR, status);
803 write_4(sc, EMAC_IER, (RCOMP_INTERRUPT|RXUBR_INTERRUPT));
844 write_4(sc, EMAC_IDR, (RCOMP_INTERRUPT|RXUBR_INTERRUPT));
1000 write_4(sc, EMAC_NCR, read_4(sc, EMAC_NCR) | TRANSMIT_START);
1110 write_4(sc, EMAC_HRB, 0);
1111 write_4(sc, EMAC_HRT, 0);
1115 write_4(sc, EMAC_HRB, ~0);
1116 write_4(sc, EMAC_HRT, ~0);
1122 write_4(sc, EMAC_NCFGR, config);
1139 write_4(sc, EMAC_HRB, multicast_filter[0]);
1140 write_4(sc, EMAC_HRT, multicast_filter[1]);
1141 write_4(sc, EMAC_NCFGR, config|CFG_MTI);
1249 write_4(sc, EMAC_NCR, 0);
1251 write_4(sc, EMAC_NCR, CLEAR_STAT);
1254 write_4(sc, EMAC_TSR, ~0UL);
1255 write_4(sc, EMAC_RSR, ~0UL);
1258 write_4(sc, EMAC_IDR, ~0UL);
1350 write_4(sc, EMAC_NCFGR, sc->clock);
1351 write_4(sc, EMAC_USRIO, USRIO_CLOCK); //enable clock
1353 write_4(sc, EMAC_NCR, MPE_ENABLE); //enable MPE
1447 write_4(sc, EMAC_MAN, EMAC_MAN_REG_RD(phy, reg));
1459 write_4(sc, EMAC_MAN, EMAC_MAN_REG_WR(phy, reg, data));
1524 write_4(sc, EMAC_NCFGR, config);