Target/Hexagon/HexagonHardwareLoops.cpp

326   MachineBasicBlock *Latch = L->getLoopLatch();
327   if (!Header || !Preheader || !Latch)
351       if (Phi->getOperand(i+1).getMBB() != Latch)
374   bool NotAnalyzed = TII->AnalyzeBranch(*Latch, TB, FB, Cond, false);
455   MachineBasicBlock *Latch = L->getLoopLatch();
456   if (!Latch)
474     else if (MBB == Latch)
482   bool NotAnalyzed = TII->AnalyzeBranch(*Latch, TB, FB, Cond, false);
490   assert (TB && "Latch block without a branch?");
1247   MachineBasicBlock *Latch = L->getLoopLatch();
1249   if (!Header || !Preheader || !Latch)
1271       if (Phi->getOperand(i+1).getMBB() != Latch)
1298   bool NotAnalyzed = TII->AnalyzeBranch(*Latch, TB, FB, Cond, false);
1419   MachineBasicBlock *Latch = L->getLoopLatch();
1423   if (!Latch || Header->hasAddressTaken())
1435   if (TII->AnalyzeBranch(*Latch, TB, FB, Tmp1, false))
1440     if (PB != Latch) {
1474         if (PredB == Latch)
1485         if (PredB != Latch) {
1507         if (MO.getMBB() != Latch)
1523     if (PB != Latch) {
1537   bool LatchNotAnalyzed = TII->AnalyzeBranch(*Latch, TB, FB, Tmp2, false);
1541     TII->InsertBranch(*Latch, Header, 0, EmptyCond, DL);