ARM/AsmParser/ARMAsmParser.cpp

6999     unsigned newOpc;
7002     case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
7003     case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
7004     case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
7005     case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR   : ARM::t2RORrr; break;
7007     TmpInst.setOpcode(newOpc);
7033     unsigned newOpc;
7036     case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
7037     case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
7038     case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
7039     case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
7040     case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
7044     TmpInst.setOpcode(newOpc);
7050     if (newOpc != ARM::t2RRX)
7482     unsigned newOpc;
7487     case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7488     case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7489     case ARM::EORrsi: newOpc = ARM::EORrr; break;
7490     case ARM::BICrsi: newOpc = ARM::BICrr; break;
7491     case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7492     case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7499       TmpInst.setOpcode(newOpc);