binutils/opcodes/alpha-opc.c

58 /* The RB field when it is the same as the RA field in the same insn.
60    the RA field into the RB field, and the extraction function just
209 #define RA		(UNUSED + 1)
211 #define RB		(RA + 1)
241   /* The RB field when it must be the same as the RA field.  */
249   /* The RC field when it can *default* to RA.  */
259   /* The FC field when it can *default* to RA.  */
413 #define ARG_BRA			{ RA, BDISP }
417 #define ARG_MEM			{ RA, MDISP, PRB }
419 #define ARG_OPR			{ RA, RB, DRC1 }
420 #define ARG_OPRL		{ RA, LIT, DRC1 }
424 #define ARG_EV4HWMEM		{ RA, EV4HWDISP, PRB }
425 #define ARG_EV4HWMPR		{ RA, RBA, EV4HWINDEX }
426 #define ARG_EV5HWMEM		{ RA, EV5HWDISP, PRB }
427 #define ARG_EV6HWMEM		{ RA, EV6HWDISP, PRB }
489   { "lda",		MEM(0x08), BASE, { RA, MDISP, ZB } },	/* pseudo */
491   { "ldah",		MEM(0x09), BASE, { RA, MDISP, ZB } },	/* pseudo */
570   { "mov",		OPR(0x11,0x20), BASE, { RA, RBA, RC } }, /* pseudo */
667   { "itofs",		FP(0x14,0x004), CIX, { RA, ZB, FC } },
670   { "itoff",		FP(0x14,0x014), CIX, { RA, ZB, FC } },
671   { "itoft",		FP(0x14,0x024), CIX, { RA, ZB, FC } },
1051   { "rpcc",		MFC(0x18,0xC000), BASE, { RA, ZB } },
1052   { "rpcc",		MFC(0x18,0xC000), BASE, { RA, RB } },	/* ev6 una */
1053   { "rc",		MFC(0x18,0xE000), BASE, { RA } },
1055   { "rs",		MFC(0x18,0xF000), BASE, { RA } },
1059   { "hw_mfpr",		OPR(0x19,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } },
1060   { "hw_mfpr",		OP(0x19), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } },
1061   { "hw_mfpr",		OP(0x19), OP_MASK, EV6, { RA, ZB, EV6HWINDEX } },
1073   { "jmp",		MBR(0x1A,0), BASE, { RA, CPRB, JMPHINT } },
1074   { "jsr",		MBR(0x1A,1), BASE, { RA, CPRB, JMPHINT } },
1077   { "ret",		MBR(0x1A,2), BASE, { RA, CPRB, RETHINT } },
1078   { "jcr",		MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } }, /* alias */
1079   { "jsr_coroutine",	MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } },
1318   { "hw_mtpr",		OPR(0x1D,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } },
1319   { "hw_mtpr",		OP(0x1D), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } },