gas/config/tc-score.c

47 #define BAD_ARGS 	          _("bad arguments to instruction")
49 #define BAD_COND 	          _("instruction is not conditional")
53 #define ERR_FOR_SCORE5U_ATOMIC    _("This architecture doesn't support atomic instruction")
56 #define BAD_GARBAGE               _("garbage following instruction");
123 /* Default will do instruction relax, -O0 will set g_opt = 0.  */
141   unsigned long instruction;
753   /* Macro instruction.  */
871           inst.instruction |= reg << shift;
927       if ((((inst.instruction >> 15) & 0x10) == 0)
928           && (((inst.instruction >> 10) & 0x10) == 0)
929           && (((inst.instruction >> 20) & 0x10) == 0)
931           && (((inst.instruction >> 20) & 0xf) == ((inst.instruction >> 15) & 0xf)))
933           inst.relax_inst |= (((inst.instruction >> 10) & 0xf) << 4)
934             | (((inst.instruction >> 15) & 0xf) << 8);
1248                 inst.instruction |= 0x8000000;
1249                 inst.instruction |= ((inst.reloc.exp.X_add_number >> 16) << 1) & 0x1fffe;
1284       inst.instruction |= value << shift;
1287   if ((inst.instruction & 0xf0000000) == 0x30000000)
1289       if ((((inst.instruction >> 20) & 0x1F) != 0)
1290           && (((inst.instruction >> 20) & 0x1F) != 1)
1291           && (((inst.instruction >> 20) & 0x1F) != 2)
1292           && (((inst.instruction >> 20) & 0x1F) != 3)
1293           && (((inst.instruction >> 20) & 0x1F) != 4)
1294           && (((inst.instruction >> 20) & 0x1F) != 8)
1295           && (((inst.instruction >> 20) & 0x1F) != 9)
1296           && (((inst.instruction >> 20) & 0x1F) != 0xa)
1297           && (((inst.instruction >> 20) & 0x1F) != 0xb)
1298           && (((inst.instruction >> 20) & 0x1F) != 0xc)
1299           && (((inst.instruction >> 20) & 0x1F) != 0xd)
1300           && (((inst.instruction >> 20) & 0x1F) != 0xe)
1301           && (((inst.instruction >> 20) & 0x1F) != 0x10)
1302           && (((inst.instruction >> 20) & 0x1F) != 0x11)
1303           && (((inst.instruction >> 20) & 0x1F) != 0x18)
1304           && (((inst.instruction >> 20) & 0x1F) != 0x1A)
1305           && (((inst.instruction >> 20) & 0x1F) != 0x1B)
1306           && (((inst.instruction >> 20) & 0x1F) != 0x1d)
1307           && (((inst.instruction >> 20) & 0x1F) != 0x1e)
1308           && (((inst.instruction >> 20) & 0x1F) != 0x1f))
1332   if ((inst.instruction & 0x20c0000) == 0x20c0000)
1334       if ((((inst.instruction >> 20) & 0x10) == 0x10) || ((inst.instruction & 0x1fe00) != 0))
1340           inst.relax_inst |= (inst.instruction >> 1) & 0xff;
1341           inst.relax_inst |= (((inst.instruction >> 20) & 0xf) << 8);
1345   else if (((inst.instruction >> 20) & 0x10) == 0x10)
1406   if ((((inst.instruction >> 20) & 0x1f) == ((inst.instruction >> 15) & 0x1f))
1407       && (inst.relax_inst != 0x8000) && (((inst.instruction >> 15) & 0x10) == 0))
1409       inst.relax_inst |= (((inst.instruction >> 10) & 0x1f) << 3) | (((inst.instruction >> 15) & 0xf) << 8);
1443   if ((inst.relax_inst != 0x8000) && (((inst.instruction >> 15) & 0x10) == 0))
1445       inst.relax_inst |= (((inst.instruction >> 10) & 0x1f) << 3) | (((inst.instruction >> 15) & 0xf) << 8);
1464   if (((inst.instruction & 0xa0dfffe) != 0xa0c0000) || ((((inst.instruction >> 20) & 0x1f) & 0x10) == 0x10))
1552   if ((inst.relax_inst != 0x8000) && (((inst.instruction >> 15) & 0x10) == 0))
1554       inst.relax_inst |= (((inst.instruction >> 10) & 0xf) << 8) | (((inst.instruction >> 15) & 0xf) << 4);
1580       inst.relax_inst |= (((inst.instruction >> 15) & 0x1f) << 3);
1598       if (((inst.instruction & 0x7f) == 0x56))  /* adjust mv -> mv! / mlfh! / mhfl! */
1601           if ((((inst.instruction >> 15) & 0x10) != 0x0) && (((inst.instruction >> 20) & 0x10) == 0))
1603               inst.relax_inst = 0x00000001 | (((inst.instruction >> 15) & 0xf) << 4)
1604                 | (((inst.instruction >> 20) & 0xf) << 8);
1608           else if ((((inst.instruction >> 15) & 0x10) == 0x0) && ((inst.instruction >> 20) & 0x10) != 0)
1610               inst.relax_inst = 0x00000002 | (((inst.instruction >> 15) & 0xf) << 4)
1611                 | (((inst.instruction >> 20) & 0xf) << 8);
1614           else if ((((inst.instruction >> 15) & 0x10) == 0x0) && (((inst.instruction >> 20) & 0x10) == 0))
1616               inst.relax_inst |= (((inst.instruction >> 15) & 0xf) << 4)
1617                 | (((inst.instruction >> 20) & 0xf) << 8);
1625       else if ((((inst.instruction >> 15) & 0x10) == 0x0) && (((inst.instruction >> 20) & 0x10) == 0))
1627           inst.relax_inst |= (((inst.instruction >> 15) & 0xf) << 4)
1628             | (((inst.instruction >> 20) & 0xf) << 8);
1658   if ((inst.instruction & 0xff) == 0x50)
1686   if ((inst.relax_inst != 0x8000) && (((inst.instruction >> 10) & 0x10) == 0)
1687       && (((inst.instruction >> 20) & 0x10) == 0))
1689       inst.relax_inst |= (((inst.instruction >> 10) & 0xf) << 4) | (((inst.instruction >> 20) & 0xf) << 8);
1708   if ((inst.relax_inst != 0x8000) && (((inst.instruction >> 20) & 0x1f) == 3)
1709       && (((inst.instruction >> 10) & 0x10) == 0) && (((inst.instruction >> 15) & 0x10) == 0))
1711       inst.relax_inst |= (((inst.instruction >> 10) & 0xf) << 4) | (((inst.instruction >> 15) & 0xf) << 8);
1764             inst.instruction |= reg << shift;
1792       if ((inst.instruction & 0x700f) == 0x2003)        /* cmp!  */
1794           inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 15)
1795             | (((inst.instruction >> 4) & 0xf) << 10);
1797       else if ((inst.instruction & 0x700f) == 0x2006)   /* not!  */
1799 	  inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 20)
1800 	    | (((inst.instruction >> 4) & 0xf) << 15);
1804           inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 20)
1805             | (((inst.instruction >> 8) & 0xf) << 15) | (((inst.instruction >> 4) & 0xf) << 10);
1842       inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 10)
1843                       | (((inst.instruction >> 4) & 0xf) << 15);
1860             inst.instruction |= (reg & 0xf) << shift;
1883       inst.relax_inst |= ((((inst.instruction >> 8) & 0xf) | 0x10) << 20)
1884         | (((inst.instruction >> 4) & 0xf) << 15) | (0xf << 10);
1900       inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 20)
1901         | ((((inst.instruction >> 4) & 0xf) | 0x10) << 15) | (0xf << 10);
1910    a data instruction.  We do this by pushing the expression into a symbol
2007   md_number_to_chars (p, one_inst.instruction, one_inst.size);
2037   nop_inst.instruction = 0x0000;
2043   pflush_inst.instruction = 0x8000800a;
2056   /* Push current instruction to dependency_vector[0].  */
2062   /* There is no dependency between nop and any instruction.  */
2253       /* FIXME.  at this time, INSN_CLASS_SYN must be 32 bit, but, instruction type should
2254          be changed if macro instruction has been expanded.  */
2284   /* Adjust instruction opcode and to be relaxed instruction opcode.  */
2287       backup_inst1.instruction = ((backup_inst1.instruction & 0x7FFF) << 15)
2288                                   | (inst2->instruction & 0x7FFF);
2289       backup_inst1.instruction = adjust_paritybit (backup_inst1.instruction, INSN_CLASS_PCE);
2297       backup_inst1.instruction = adjust_paritybit (backup_inst1.instruction,
2312   /* Start a new frag if frag_now is not empty and is not instruction frag, maybe it contains
2313      data produced by .ascii etc.  Doing this is to make one instruction per frag.  */
2322   /* Here, we must call frag_grow in order to keep the instruction frag type is
2331   md_number_to_chars (p, backup_inst1.instruction, backup_inst1.size);
2400       inst.instruction = opcode->value;
2413       /* It indicates current instruction is a macro instruction if inst.bwarn equals -1.  */
2465               inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 20)
2466                 | (((inst.instruction >> 4) & 0xf) << 15) | (0xf << 10);
2476               /* Set bwarn as -1, so macro instruction itself will not be generated frag.  */
2496               /* Set bwarn as -1, so macro instruction itself will not be generated frag.  */
2517       if (((inst.instruction >> 3) & 0x10) == 0)        /* for judge is addei or subei : bit 5 =0 : addei */
2519           if (((inst.instruction >> 3) & 0xf) != 0xf)
2521               inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 20)
2522                 | ((1 << ((inst.instruction >> 3) & 0xf)) << 1);
2532           if (((inst.instruction >> 3) & 0xf) != 0xf)
2534               inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 20)
2535                 | (((-(1 << ((inst.instruction >> 3) & 0xf))) & 0xffff) << 1);
2558       inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 20)
2559         | (((inst.instruction >> 8) & 0xf) << 15) | (((inst.instruction >> 3) & 0x1f) << 10);
2574       inst.relax_inst |= (((inst.instruction >> 3) & 0x1f) << 15);
2671       inst.instruction |= value << shift;
2730                       unsigned int ldst_func = inst.instruction & OPC_PSEUDOLDST_MASK;
2743                   ldst_idx = inst.instruction & OPC_PSEUDOLDST_MASK;
2744                   inst.instruction &= ~OPC_PSEUDOLDST_MASK;
2745                   inst.instruction |= score_ldst_insns[ldst_idx * 3 + LDST_POST].value;
2748                   if ((inst.instruction & 0x3e000007) == 0x0e000000)
2751                       if ((((inst.instruction >> 15) & 0x18) == 0)
2752                           && (((inst.instruction >> 3) & 0xfff) == 4))
2755                           if ((((inst.instruction >> 20) & 0x10) == 0x10))
2757                               inst.relax_inst = 0x0000200a | (((inst.instruction >> 20) & 0xf)
2759                                 (((inst.instruction >> 15) & 0x7) << 4);
2764                               inst.relax_inst = 0x0000200a | (((inst.instruction >> 20) & 0xf)
2766                                 (((inst.instruction >> 15) & 0x7) << 4);
2785                   ldst_idx = inst.instruction & OPC_PSEUDOLDST_MASK;
2786                   inst.instruction &= ~OPC_PSEUDOLDST_MASK;
2787                   inst.instruction |= score_ldst_insns[ldst_idx * 3 + pre_inc].value;
2788                   inst.instruction |= value << 3;
2799               ldst_idx = inst.instruction & OPC_PSEUDOLDST_MASK;
2800               inst.instruction &= ~OPC_PSEUDOLDST_MASK;
2801               inst.instruction |= score_ldst_insns[ldst_idx * 3 + LDST_NOUPDATE].value;
2833               /* lw/lh/lbu/sw/sh/sb, offset = 0, relax to 16 bit instruction.  */
2839                   if ((((inst.instruction >> 15) & 0x10) == 0) && (((inst.instruction >> 20) & 0x10) == 0))
2841                       inst.relax_inst |= (2 << 12) | (((inst.instruction >> 20) & 0xf) << 8) |
2842                         (((inst.instruction >> 15) & 0xf) << 4);
2877                   unsigned int ldst_func = inst.instruction & OPC_PSEUDOLDST_MASK;
2942               ldst_idx = inst.instruction & OPC_PSEUDOLDST_MASK;
2943               inst.instruction &= ~OPC_PSEUDOLDST_MASK;
2944               inst.instruction |= score_ldst_insns[ldst_idx * 3 + pre_inc].value;
2946                 inst.instruction |= value << 3;
2948                 inst.instruction |= value;
2951               if ((inst.instruction & 0x3e000000) == 0x20000000)
2954                   if ((((inst.instruction >> 15) & 0x10) == 0)
2955                       && (((inst.instruction >> 20) & 0x10) == 0))
2958                       if ((inst.instruction & 0x7fff) == 0)
2960                           inst.relax_inst |= (((inst.instruction >> 15) & 0xf) << 4)
2961                             | (((inst.instruction >> 20) & 0xf) << 8);
2965                       else if ((((inst.instruction >> 15) & 0xf) == 2)
2966                                && ((inst.instruction & 0x3) == 0)
2967                                && ((inst.instruction & 0x7fff) < 128))
2969                           inst.relax_inst = 0x7000 | (((inst.instruction >> 20) & 0xf) << 8)
2970                             | (((inst.instruction & 0x7fff) >> 2) << 3);
2984               else if ((inst.instruction & 0x3e000000) == 0x28000000)
2987                   if ((((inst.instruction >> 15) & 0x10) == 0) && (((inst.instruction >> 20) & 0x10) == 0))
2990                       if ((inst.instruction & 0x7fff) == 0)
2992                           inst.relax_inst |= (((inst.instruction >> 15) & 0xf) << 4)
2993                             | (((inst.instruction >> 20) & 0xf) << 8);
2997                       else if ((((inst.instruction >> 15) & 0xf) == 2)
2998                                && ((inst.instruction & 0x3) == 0)
2999                                && ((inst.instruction & 0x7fff) < 128))
3001                           inst.relax_inst = 0x7004 | (((inst.instruction >> 20) & 0xf) << 8)
3002                             | (((inst.instruction & 0x7fff) >> 2) << 3);
3016               else if ((inst.instruction & 0x3e000007) == 0x06000004)
3019                   if ((((inst.instruction >> 15) & 0x18) == 0)
3020                       && (((inst.instruction >> 3) & 0xfff) == 0xffc))
3023                       if ((((inst.instruction >> 20) & 0x10) == 0x10))
3025                           inst.relax_inst = 0x0000200e | (((inst.instruction >> 20) & 0xf) << 8)
3026                             | 1 << 7 | (((inst.instruction >> 15) & 0x7) << 4);
3032                           inst.relax_inst = 0x0000200e | (((inst.instruction >> 20) & 0xf) << 8)
3033                             | 0 << 7 | (((inst.instruction >> 15) & 0x7) << 4);
3043               else if ((inst.instruction & 0x3e000000) == 0x22000000)
3046                   if ((((inst.instruction >> 15) & 0x10) == 0) && (((inst.instruction >> 20) & 0x10) == 0))
3049                       if ((inst.instruction & 0x7fff) == 0)
3051                           inst.relax_inst |= (((inst.instruction >> 15) & 0xf) << 4)
3052                             | (((inst.instruction >> 20) & 0xf) << 8);
3056                       else if ((((inst.instruction >> 15) & 0xf) == 2)
3057                                && ((inst.instruction & 0x1) == 0)
3058                                && ((inst.instruction & 0x7fff) < 64))
3060                           inst.relax_inst = 0x7001 | (((inst.instruction >> 20) & 0xf) << 8)
3061                             | (((inst.instruction & 0x7fff) >> 1) << 3);
3075               else if ((inst.instruction & 0x3e000000) == 0x2a000000)
3078                   if ((((inst.instruction >> 15) & 0x10) == 0) && (((inst.instruction >> 20) & 0x10) == 0))
3081                       if ((inst.instruction & 0x7fff) == 0)
3083                           inst.relax_inst |= (((inst.instruction >> 15) & 0xf) << 4)
3084                             | (((inst.instruction >> 20) & 0xf) << 8);
3088                       else if ((((inst.instruction >> 15) & 0xf) == 2)
3089                                && ((inst.instruction & 0x1) == 0)
3090                                && ((inst.instruction & 0x7fff) < 64))
3092                           inst.relax_inst = 0x7005 | (((inst.instruction >> 20) & 0xf) << 8)
3093                             | (((inst.instruction & 0x7fff) >> 1) << 3);
3107               else if ((inst.instruction & 0x3e000000) == 0x2c000000)
3110                   if ((((inst.instruction >> 15) & 0x10) == 0) && (((inst.instruction >> 20) & 0x10) == 0))
3113                       if ((inst.instruction & 0x7fff) == 0)
3115                           inst.relax_inst |= (((inst.instruction >> 15) & 0xf) << 4)
3116                             | (((inst.instruction >> 20) & 0xf) << 8);
3120                       else if ((((inst.instruction >> 15) & 0xf) == 2)
3121                                && ((inst.instruction & 0x7fff) < 32))
3123                           inst.relax_inst = 0x7003 | (((inst.instruction >> 20) & 0xf) << 8)
3124                             | ((inst.instruction & 0x7fff) << 3);
3138               else if ((inst.instruction & 0x3e000000) == 0x2e000000)
3141                   if ((((inst.instruction >> 15) & 0x10) == 0) && (((inst.instruction >> 20) & 0x10) == 0))
3144                       if ((inst.instruction & 0x7fff) == 0)
3146                           inst.relax_inst |= (((inst.instruction >> 15) & 0xf) << 4)
3147                             | (((inst.instruction >> 20) & 0xf) << 8);
3151                       else if ((((inst.instruction >> 15) & 0xf) == 2)
3152                                && ((inst.instruction & 0x7fff) < 32))
3154                           inst.relax_inst = 0x7007 | (((inst.instruction >> 20) & 0xf) << 8)
3155                             | ((inst.instruction & 0x7fff) << 3);
3203       cache_op = (inst.instruction >> 20) & 0x1F;
3346               inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 20)
3347                               | (((inst.instruction >> 4) & 0xf) << 15);
3394   ldst_func = inst.instruction & LDST16_RI_MASK;
3408       if ((inst.instruction & 0x7000) == N16_LIU)
3410           inst.relax_inst |= ((inst.instruction >> 8) & 0xf) << 20
3411                           | ((inst.instruction & 0xff) << 1);
3413       else if (((inst.instruction & 0x7007) == N16_LHP)
3414                || ((inst.instruction & 0x7007) == N16_SHP))
3416           inst.relax_inst |= ((inst.instruction >> 8) & 0xf) << 20 | 2 << 15
3417                           | (((inst.instruction >> 3) & 0x1f) << 1);
3419       else if (((inst.instruction & 0x7007) == N16_LWP)
3420                || ((inst.instruction & 0x7007) == N16_SWP))
3422           inst.relax_inst |= ((inst.instruction >> 8) & 0xf) << 20 | 2 << 15
3423                           | (((inst.instruction >> 3) & 0x1f) << 2);
3425       else if (((inst.instruction & 0x7007) == N16_LBUP)
3426                || ((inst.instruction & 0x7007) == N16_SBP))
3428           inst.relax_inst |= ((inst.instruction >> 8) & 0xf) << 20 | 2 << 15
3429                           | (((inst.instruction >> 3) & 0x1f));
3451   inst.instruction &= ~(1 << 12);
3453   inst.instruction |= H_bit_mask << 7;
3481       if ((inst.instruction & 0xf) == 0xa)
3485               inst.relax_inst |= ((((inst.instruction >> 8) & 0xf) | 0x10) << 20)
3486                                   | (((inst.instruction >> 4) & 0x7) << 15) | (4 << 3);
3490               inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 20)
3491                                   | (((inst.instruction >> 4) & 0x7) << 15) | (4 << 3);
3499               inst.relax_inst |= ((((inst.instruction >> 8) & 0xf) | 0x10) << 20)
3500                                   | (((inst.instruction >> 4) & 0x7) << 15) | (((-4) & 0xfff) << 3);
3504               inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 20)
3505                                   | (((inst.instruction >> 4) & 0x7) << 15) | (((-4) & 0xfff) << 3);
3581               unsigned int ldst_func = inst.instruction & LDST_UNALIGN_MASK;
3674   /* Adjust instruction opcode and to be relaxed instruction opcode.  */
3675   inst_main.instruction = adjust_paritybit (inst_main.instruction, GET_INSN_CLASS (inst_main.type));
3681       var_insts[i].instruction = adjust_paritybit (var_insts[i].instruction,
3701   md_number_to_chars (p, inst_main.instruction, inst_main.size);
3749       md_number_to_chars (p, var_insts[i].instruction, var_insts[i].size);
3752   /* Set bwarn as -1, so macro instruction itself will not be generated frag.  */
3756 /* Build a relax frag for la instruction when generating PIC,
3892      /* Set bwarn as -1, so macro instruction itself will not be generated frag.  */
3950               /* Set bwarn as -1, so macro instruction itself will not be generated frag.  */
3993               inst.error = _("li rd label isn't correct instruction form");
4008                   /* Set bwarn as -1, so macro instruction itself will not be generated frag.  */
4090           /* Set bwarn as -1, so macro instruction itself will not be generated frag.  */
4182 /* Build a relax frag for lw/st instruction when generating PIC,
4234       /* Set bwarn as -1, so macro instruction itself will not be generated frag.  */
4323           ldst_idx = inst.instruction & OPC_PSEUDOLDST_MASK;
4336               ldst_idx = inst.instruction & OPC_PSEUDOLDST_MASK;
4337               inst.instruction &= ~OPC_PSEUDOLDST_MASK;
4338               inst.instruction |= score_ldst_insns[ldst_idx * 3 + 0].value;
4339               inst.instruction |= reg_rd << 20;
4340               inst.instruction |= GP << 15;
4373       /* Adjust instruction opcode and to be relaxed instruction opcode.  */
4374       inst_main.instruction = adjust_paritybit (inst_main.instruction, GET_INSN_CLASS (inst_main.type));
4379 	inst_expand[i].instruction = adjust_paritybit (inst_expand[i].instruction
4397       md_number_to_chars (p, inst_main.instruction, inst_main.size);
4409       /* GP instruction can not do optimization, only can do relax between
4410          1 instruction and 3 instructions.  */
4417       md_number_to_chars (p, inst_expand[0].instruction, inst_expand[0].size);
4419       md_number_to_chars (p, inst_expand[1].instruction, inst_expand[1].size);
4421       md_number_to_chars (p, inst_expand[2].instruction, inst_expand[2].size);
4431   /* Set bwarn as -1, so macro instruction itself will not be generated frag.  */
4458       inst.instruction |= GP << 15;
4469       if (((inst.instruction & 0x3e0003ff) == 0x0c000004)
4470           || ((inst.instruction & 0x3e0003ff) == 0x0c000024)
4471           || ((inst.instruction & 0x3e0003ff) == 0x0c000044)
4472           || ((inst.instruction & 0x3e0003ff) == 0x0c000064))
4575   inst.instruction |= (inst.reloc.exp.X_add_number & 0x3fe) | ((inst.reloc.exp.X_add_number & 0xffc00) << 5);
4577   /* Compute 16 bit branch instruction.  */
4580       inst.relax_inst |= (((inst.instruction >> 10) & 0xf) << 8);
4611       inst.instruction |= ((inst.reloc.exp.X_add_number >> 1) & 0xff);
4615 /* Iterate over the base tables to create the instruction patterns.  */
4841       /* Only at the first time determining whether GP instruction relax should be done,
4842          return the difference between insntruction size and instruction relax size.  */
4854 /* In this function, we determine whether GP instruction should do relaxation,
4943   /* If the instruction address is odd, make it half word align first.  */
4955   /* Get instruction size and relax size after the last relaxation.  */
4967   /* Handle specially for GP instruction.  for, judge_size_before_relax() has already determine
4968      whether the GP instruction should do relax.  */
5508       /* Update instruction imm bit.  */
5640       inst.error = _("pce instruction error (16 bit || 16 bit)'");
5666    instruction in the error message.  */