Lines Matching defs:inst
28 #include "opcode/score-inst.h"
88 #define SET_INSN_ERROR(s) (inst.error = (s))
157 struct score_it inst;
260 struct score_it *inst;
807 if (!inst.error)
808 inst.error = BAD_GARBAGE;
856 if ((reg == 1) && (nor1 == 1) && (inst.bwarn == 0))
859 inst.bwarn = 1;
865 strcpy (inst.reg, score_crn_table[reg].name);
867 strcpy (inst.reg, score_srn_table[reg].name);
869 strcpy (inst.reg, "");
871 inst.instruction |= reg << shift;
878 inst.error = buff;
896 inst.error = BAD_SKIP_COMMA;
903 inst.error = BAD_SKIP_COMMA;
927 if ((((inst.instruction >> 15) & 0x10) == 0)
928 && (((inst.instruction >> 10) & 0x10) == 0)
929 && (((inst.instruction >> 20) & 0x10) == 0)
930 && (inst.relax_inst != 0x8000)
931 && (((inst.instruction >> 20) & 0xf) == ((inst.instruction >> 15) & 0xf)))
933 inst.relax_inst |= (((inst.instruction >> 10) & 0xf) << 4)
934 | (((inst.instruction >> 15) & 0xf) << 8);
935 inst.relax_size = 2;
939 inst.relax_inst = 0x8000;
974 inst.error = _("illegal expression");
985 inst.error = _("invalid constant");
992 && (inst.type != PC_DISP19div2)
993 && (inst.type != PC_DISP8div2)
994 && (inst.type != PC_DISP24div2)
995 && (inst.type != PC_DISP11div2)
996 && (inst.type != Insn_Type_SYN)
997 && (inst.type != Rd_rvalueRs_SI15)
998 && (inst.type != Rd_lvalueRs_SI15)
999 && (inst.type != Insn_internal))
1001 inst.error = BAD_ARGS;
1106 inst.error = NULL;
1124 if (my_get_expression (&inst.reloc.exp, &pp) == (int) FAIL)
1127 if (inst.error != 0)
1133 if (my_get_expression (&inst.reloc.exp, str) == (int) FAIL)
1173 if ((inst.reloc.exp.X_add_number == 0)
1174 && (inst.type != Insn_Type_SYN)
1175 && (inst.type != Rd_rvalueRs_SI15)
1176 && (inst.type != Rd_lvalueRs_SI15)
1177 && (inst.type != Insn_internal)
1183 inst.error = BAD_ARGS;
1188 if ((inst.reloc.exp.X_add_symbol)
1201 inst.error = BAD_ARGS;
1205 if (inst.reloc.exp.X_add_symbol)
1212 inst.reloc.type = BFD_RELOC_HI16_S;
1213 inst.reloc.pc_rel = 0;
1216 inst.reloc.type = BFD_RELOC_LO16;
1217 inst.reloc.pc_rel = 0;
1220 inst.reloc.type = BFD_RELOC_SCORE_GPREL15;
1221 inst.reloc.pc_rel = 0;
1225 inst.reloc.type = BFD_RELOC_SCORE_GOT_LO16;
1226 inst.reloc.pc_rel = 0;
1229 inst.reloc.type = BFD_RELOC_32;
1230 inst.reloc.pc_rel = 0;
1238 inst.reloc.type = BFD_RELOC_SCORE_DUMMY_HI16;
1239 inst.reloc.pc_rel = 0;
1242 if (data_type == _SIMM16_LA && inst.reloc.exp.X_unsigned == 1)
1244 value = validate_immediate (inst.reloc.exp.X_add_number, _SIMM16_LA_POS, hex_p);
1246 if ((inst.reloc.exp.X_add_number & 0xffff) == 0)
1248 inst.instruction |= 0x8000000;
1249 inst.instruction |= ((inst.reloc.exp.X_add_number >> 16) << 1) & 0x1fffe;
1255 value = validate_immediate (inst.reloc.exp.X_add_number, data_type, hex_p);
1275 inst.error = err_msg;
1284 inst.instruction |= value << shift;
1287 if ((inst.instruction & 0xf0000000) == 0x30000000)
1289 if ((((inst.instruction >> 20) & 0x1F) != 0)
1290 && (((inst.instruction >> 20) & 0x1F) != 1)
1291 && (((inst.instruction >> 20) & 0x1F) != 2)
1292 && (((inst.instruction >> 20) & 0x1F) != 3)
1293 && (((inst.instruction >> 20) & 0x1F) != 4)
1294 && (((inst.instruction >> 20) & 0x1F) != 8)
1295 && (((inst.instruction >> 20) & 0x1F) != 9)
1296 && (((inst.instruction >> 20) & 0x1F) != 0xa)
1297 && (((inst.instruction >> 20) & 0x1F) != 0xb)
1298 && (((inst.instruction >> 20) & 0x1F) != 0xc)
1299 && (((inst.instruction >> 20) & 0x1F) != 0xd)
1300 && (((inst.instruction >> 20) & 0x1F) != 0xe)
1301 && (((inst.instruction >> 20) & 0x1F) != 0x10)
1302 && (((inst.instruction >> 20) & 0x1F) != 0x11)
1303 && (((inst.instruction >> 20) & 0x1F) != 0x18)
1304 && (((inst.instruction >> 20) & 0x1F) != 0x1A)
1305 && (((inst.instruction >> 20) & 0x1F) != 0x1B)
1306 && (((inst.instruction >> 20) & 0x1F) != 0x1d)
1307 && (((inst.instruction >> 20) & 0x1F) != 0x1e)
1308 && (((inst.instruction >> 20) & 0x1F) != 0x1f))
1310 inst.error = _("invalid constant: bit expression not defined");
1332 if ((inst.instruction & 0x20c0000) == 0x20c0000)
1334 if ((((inst.instruction >> 20) & 0x10) == 0x10) || ((inst.instruction & 0x1fe00) != 0))
1336 inst.relax_inst = 0x8000;
1340 inst.relax_inst |= (inst.instruction >> 1) & 0xff;
1341 inst.relax_inst |= (((inst.instruction >> 20) & 0xf) << 8);
1342 inst.relax_size = 2;
1345 else if (((inst.instruction >> 20) & 0x10) == 0x10)
1347 inst.relax_inst = 0x8000;
1406 if ((((inst.instruction >> 20) & 0x1f) == ((inst.instruction >> 15) & 0x1f))
1407 && (inst.relax_inst != 0x8000) && (((inst.instruction >> 15) & 0x10) == 0))
1409 inst.relax_inst |= (((inst.instruction >> 10) & 0x1f) << 3) | (((inst.instruction >> 15) & 0xf) << 8);
1410 inst.relax_size = 2;
1413 inst.relax_inst = 0x8000;
1443 if ((inst.relax_inst != 0x8000) && (((inst.instruction >> 15) & 0x10) == 0))
1445 inst.relax_inst |= (((inst.instruction >> 10) & 0x1f) << 3) | (((inst.instruction >> 15) & 0xf) << 8);
1446 inst.relax_size = 2;
1449 inst.relax_inst = 0x8000;
1464 if (((inst.instruction & 0xa0dfffe) != 0xa0c0000) || ((((inst.instruction >> 20) & 0x1f) & 0x10) == 0x10))
1465 inst.relax_inst = 0x8000;
1467 inst.relax_size = 2;
1552 if ((inst.relax_inst != 0x8000) && (((inst.instruction >> 15) & 0x10) == 0))
1554 inst.relax_inst |= (((inst.instruction >> 10) & 0xf) << 8) | (((inst.instruction >> 15) & 0xf) << 4);
1555 inst.relax_size = 2;
1558 inst.relax_inst = 0x8000;
1578 if (inst.relax_inst != 0x8000)
1580 inst.relax_inst |= (((inst.instruction >> 15) & 0x1f) << 3);
1581 inst.relax_size = 2;
1596 if (inst.relax_inst != 0x8000)
1598 if (((inst.instruction & 0x7f) == 0x56)) /* adjust mv -> mv! / mlfh! / mhfl! */
1601 if ((((inst.instruction >> 15) & 0x10) != 0x0) && (((inst.instruction >> 20) & 0x10) == 0))
1603 inst.relax_inst = 0x00000001 | (((inst.instruction >> 15) & 0xf) << 4)
1604 | (((inst.instruction >> 20) & 0xf) << 8);
1605 inst.relax_size = 2;
1608 else if ((((inst.instruction >> 15) & 0x10) == 0x0) && ((inst.instruction >> 20) & 0x10) != 0)
1610 inst.relax_inst = 0x00000002 | (((inst.instruction >> 15) & 0xf) << 4)
1611 | (((inst.instruction >> 20) & 0xf) << 8);
1612 inst.relax_size = 2;
1614 else if ((((inst.instruction >> 15) & 0x10) == 0x0) && (((inst.instruction >> 20) & 0x10) == 0))
1616 inst.relax_inst |= (((inst.instruction >> 15) & 0xf) << 4)
1617 | (((inst.instruction >> 20) & 0xf) << 8);
1618 inst.relax_size = 2;
1622 inst.relax_inst = 0x8000;
1625 else if ((((inst.instruction >> 15) & 0x10) == 0x0) && (((inst.instruction >> 20) & 0x10) == 0))
1627 inst.relax_inst |= (((inst.instruction >> 15) & 0xf) << 4)
1628 | (((inst.instruction >> 20) & 0xf) << 8);
1629 inst.relax_size = 2;
1633 inst.relax_inst = 0x8000;
1658 if ((inst.instruction & 0xff) == 0x50)
1686 if ((inst.relax_inst != 0x8000) && (((inst.instruction >> 10) & 0x10) == 0)
1687 && (((inst.instruction >> 20) & 0x10) == 0))
1689 inst.relax_inst |= (((inst.instruction >> 10) & 0xf) << 4) | (((inst.instruction >> 20) & 0xf) << 8);
1690 inst.relax_size = 2;
1693 inst.relax_inst = 0x8000;
1708 if ((inst.relax_inst != 0x8000) && (((inst.instruction >> 20) & 0x1f) == 3)
1709 && (((inst.instruction >> 10) & 0x10) == 0) && (((inst.instruction >> 15) & 0x10) == 0))
1711 inst.relax_inst |= (((inst.instruction >> 10) & 0xf) << 4) | (((inst.instruction >> 15) & 0xf) << 8);
1712 inst.relax_size = 2;
1715 inst.relax_inst = 0x8000;
1756 if ((reg == 1) && (nor1 == 1) && (inst.bwarn == 0))
1759 inst.bwarn = 1;
1764 inst.instruction |= reg << shift;
1773 inst.error = buff;
1792 if ((inst.instruction & 0x700f) == 0x2003) /* cmp! */
1794 inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 15)
1795 | (((inst.instruction >> 4) & 0xf) << 10);
1797 else if ((inst.instruction & 0x700f) == 0x2006) /* not! */
1799 inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 20)
1800 | (((inst.instruction >> 4) & 0xf) << 15);
1804 inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 20)
1805 | (((inst.instruction >> 8) & 0xf) << 15) | (((inst.instruction >> 4) & 0xf) << 10);
1807 inst.relax_size = 4;
1825 inst.relax_inst |= rd << 20;
1826 inst.relax_size = 4;
1842 inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 10)
1843 | (((inst.instruction >> 4) & 0xf) << 15);
1844 inst.relax_size = 4;
1860 inst.instruction |= (reg & 0xf) << shift;
1868 inst.error = buff;
1883 inst.relax_inst |= ((((inst.instruction >> 8) & 0xf) | 0x10) << 20)
1884 | (((inst.instruction >> 4) & 0xf) << 15) | (0xf << 10);
1885 inst.relax_size = 4;
1900 inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 20)
1901 | ((((inst.instruction >> 4) & 0xf) | 0x10) << 15) | (0xf << 10);
1902 inst.relax_size = 4;
2396 memset (&inst, '\0', sizeof (inst));
2397 sprintf (inst.str, "%s", insnstr);
2400 inst.instruction = opcode->value;
2401 inst.relax_inst = opcode->relax_value;
2402 inst.type = opcode->type;
2403 inst.size = GET_INSN_SIZE (inst.type);
2404 inst.relax_size = 0;
2405 inst.bwarn = 0;
2406 sprintf (inst.name, "%s", opcode->template);
2407 strcpy (inst.reg, "");
2408 inst.error = NULL;
2409 inst.reloc.type = BFD_RELOC_NONE;
2413 /* It indicates current instruction is a macro instruction if inst.bwarn equals -1. */
2414 if ((inst.bwarn != -1) && (!inst.error) && (gen_frag_p))
2415 gen_insn_frag (&inst, NULL);
2418 inst.error = _("unrecognized opcode");
2428 if (inst.error)
2431 as_bad (_("%s -- `%s'"), inst.error, inst.str);
2432 inst.error = NULL;
2465 inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 20)
2466 | (((inst.instruction >> 4) & 0xf) << 15) | (0xf << 10);
2467 inst.relax_size = 4;
2477 inst.bwarn = -1;
2497 inst.bwarn = -1;
2517 if (((inst.instruction >> 3) & 0x10) == 0) /* for judge is addei or subei : bit 5 =0 : addei */
2519 if (((inst.instruction >> 3) & 0xf) != 0xf)
2521 inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 20)
2522 | ((1 << ((inst.instruction >> 3) & 0xf)) << 1);
2523 inst.relax_size = 4;
2527 inst.relax_inst = 0x8000;
2532 if (((inst.instruction >> 3) & 0xf) != 0xf)
2534 inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 20)
2535 | (((-(1 << ((inst.instruction >> 3) & 0xf))) & 0xffff) << 1);
2536 inst.relax_size = 4;
2540 inst.relax_inst = 0x8000;
2558 inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 20)
2559 | (((inst.instruction >> 8) & 0xf) << 15) | (((inst.instruction >> 3) & 0x1f) << 10);
2560 inst.relax_size = 4;
2574 inst.relax_inst |= (((inst.instruction >> 3) & 0x1f) << 15);
2575 inst.relax_size = 4;
2588 inst.error = _("address offset must be half word alignment");
2596 inst.error = _("address offset must be word alignment");
2629 if (my_get_expression (&inst.reloc.exp, str) == (int) FAIL)
2632 if (inst.reloc.exp.X_op == O_constant)
2635 int value = validate_immediate_align (inst.reloc.exp.X_add_number, data_type);
2640 value = validate_immediate (inst.reloc.exp.X_add_number, data_type, 0);
2653 inst.error = err_msg;
2671 inst.instruction |= value << shift;
2675 inst.reloc.pc_rel = 0;
2730 unsigned int ldst_func = inst.instruction & OPC_PSEUDOLDST_MASK;
2738 inst.error = _("register same as write-back base");
2743 ldst_idx = inst.instruction & OPC_PSEUDOLDST_MASK;
2744 inst.instruction &= ~OPC_PSEUDOLDST_MASK;
2745 inst.instruction |= score_ldst_insns[ldst_idx * 3 + LDST_POST].value;
2748 if ((inst.instruction & 0x3e000007) == 0x0e000000)
2751 if ((((inst.instruction >> 15) & 0x18) == 0)
2752 && (((inst.instruction >> 3) & 0xfff) == 4))
2755 if ((((inst.instruction >> 20) & 0x10) == 0x10))
2757 inst.relax_inst = 0x0000200a | (((inst.instruction >> 20) & 0xf)
2759 (((inst.instruction >> 15) & 0x7) << 4);
2764 inst.relax_inst = 0x0000200a | (((inst.instruction >> 20) & 0xf)
2766 (((inst.instruction >> 15) & 0x7) << 4);
2768 inst.relax_size = 2;
2783 value = validate_immediate (inst.reloc.exp.X_add_number, _SIMM12, 0);
2785 ldst_idx = inst.instruction & OPC_PSEUDOLDST_MASK;
2786 inst.instruction &= ~OPC_PSEUDOLDST_MASK;
2787 inst.instruction |= score_ldst_insns[ldst_idx * 3 + pre_inc].value;
2788 inst.instruction |= value << 3;
2789 inst.relax_inst = 0x8000;
2799 ldst_idx = inst.instruction & OPC_PSEUDOLDST_MASK;
2800 inst.instruction &= ~OPC_PSEUDOLDST_MASK;
2801 inst.instruction |= score_ldst_insns[ldst_idx * 3 + LDST_NOUPDATE].value;
2806 inst.relax_inst = INSN16_LBU;
2810 inst.relax_inst = INSN16_LH;
2814 inst.relax_inst = INSN16_LW;
2818 inst.relax_inst = INSN16_SB;
2822 inst.relax_inst = INSN16_SH;
2826 inst.relax_inst = INSN16_SW;
2830 inst.relax_inst = 0x8000;
2839 if ((((inst.instruction >> 15) & 0x10) == 0) && (((inst.instruction >> 20) & 0x10) == 0))
2841 inst.relax_inst |= (2 << 12) | (((inst.instruction >> 20) & 0xf) << 8) |
2842 (((inst.instruction >> 15) & 0xf) << 4);
2843 inst.relax_size = 2;
2855 inst.error = _("pre-indexed expression expected");
2859 if (my_get_expression (&inst.reloc.exp, &str) == (int) FAIL)
2865 inst.error = _("missing ]");
2877 unsigned int ldst_func = inst.instruction & OPC_PSEUDOLDST_MASK;
2885 inst.error = _("register same as write-back base");
2894 if (inst.reloc.exp.X_op == O_constant)
2923 value = validate_immediate (inst.reloc.exp.X_add_number, data_type, 0);
2937 inst.error = err_msg;
2942 ldst_idx = inst.instruction & OPC_PSEUDOLDST_MASK;
2943 inst.instruction &= ~OPC_PSEUDOLDST_MASK;
2944 inst.instruction |= score_ldst_insns[ldst_idx * 3 + pre_inc].value;
2946 inst.instruction |= value << 3;
2948 inst.instruction |= value;
2951 if ((inst.instruction & 0x3e000000) == 0x20000000)
2954 if ((((inst.instruction >> 15) & 0x10) == 0)
2955 && (((inst.instruction >> 20) & 0x10) == 0))
2958 if ((inst.instruction & 0x7fff) == 0)
2960 inst.relax_inst |= (((inst.instruction >> 15) & 0xf) << 4)
2961 | (((inst.instruction >> 20) & 0xf) << 8);
2962 inst.relax_size = 2;
2965 else if ((((inst.instruction >> 15) & 0xf) == 2)
2966 && ((inst.instruction & 0x3) == 0)
2967 && ((inst.instruction & 0x7fff) < 128))
2969 inst.relax_inst = 0x7000 | (((inst.instruction >> 20) & 0xf) << 8)
2970 | (((inst.instruction & 0x7fff) >> 2) << 3);
2971 inst.relax_size = 2;
2975 inst.relax_inst = 0x8000;
2980 inst.relax_inst = 0x8000;
2984 else if ((inst.instruction & 0x3e000000) == 0x28000000)
2987 if ((((inst.instruction >> 15) & 0x10) == 0) && (((inst.instruction >> 20) & 0x10) == 0))
2990 if ((inst.instruction & 0x7fff) == 0)
2992 inst.relax_inst |= (((inst.instruction >> 15) & 0xf) << 4)
2993 | (((inst.instruction >> 20) & 0xf) << 8);
2994 inst.relax_size = 2;
2997 else if ((((inst.instruction >> 15) & 0xf) == 2)
2998 && ((inst.instruction & 0x3) == 0)
2999 && ((inst.instruction & 0x7fff) < 128))
3001 inst.relax_inst = 0x7004 | (((inst.instruction >> 20) & 0xf) << 8)
3002 | (((inst.instruction & 0x7fff) >> 2) << 3);
3003 inst.relax_size = 2;
3007 inst.relax_inst = 0x8000;
3012 inst.relax_inst = 0x8000;
3016 else if ((inst.instruction & 0x3e000007) == 0x06000004)
3019 if ((((inst.instruction >> 15) & 0x18) == 0)
3020 && (((inst.instruction >> 3) & 0xfff) == 0xffc))
3023 if ((((inst.instruction >> 20) & 0x10) == 0x10))
3025 inst.relax_inst = 0x0000200e | (((inst.instruction >> 20) & 0xf) << 8)
3026 | 1 << 7 | (((inst.instruction >> 15) & 0x7) << 4);
3027 inst.relax_size = 2;
3032 inst.relax_inst = 0x0000200e | (((inst.instruction >> 20) & 0xf) << 8)
3033 | 0 << 7 | (((inst.instruction >> 15) & 0x7) << 4);
3034 inst.relax_size = 2;
3039 inst.relax_inst = 0x8000;
3043 else if ((inst.instruction & 0x3e000000) == 0x22000000)
3046 if ((((inst.instruction >> 15) & 0x10) == 0) && (((inst.instruction >> 20) & 0x10) == 0))
3049 if ((inst.instruction & 0x7fff) == 0)
3051 inst.relax_inst |= (((inst.instruction >> 15) & 0xf) << 4)
3052 | (((inst.instruction >> 20) & 0xf) << 8);
3053 inst.relax_size = 2;
3056 else if ((((inst.instruction >> 15) & 0xf) == 2)
3057 && ((inst.instruction & 0x1) == 0)
3058 && ((inst.instruction & 0x7fff) < 64))
3060 inst.relax_inst = 0x7001 | (((inst.instruction >> 20) & 0xf) << 8)
3061 | (((inst.instruction & 0x7fff) >> 1) << 3);
3062 inst.relax_size = 2;
3066 inst.relax_inst = 0x8000;
3071 inst.relax_inst = 0x8000;
3075 else if ((inst.instruction & 0x3e000000) == 0x2a000000)
3078 if ((((inst.instruction >> 15) & 0x10) == 0) && (((inst.instruction >> 20) & 0x10) == 0))
3081 if ((inst.instruction & 0x7fff) == 0)
3083 inst.relax_inst |= (((inst.instruction >> 15) & 0xf) << 4)
3084 | (((inst.instruction >> 20) & 0xf) << 8);
3085 inst.relax_size = 2;
3088 else if ((((inst.instruction >> 15) & 0xf) == 2)
3089 && ((inst.instruction & 0x1) == 0)
3090 && ((inst.instruction & 0x7fff) < 64))
3092 inst.relax_inst = 0x7005 | (((inst.instruction >> 20) & 0xf) << 8)
3093 | (((inst.instruction & 0x7fff) >> 1) << 3);
3094 inst.relax_size = 2;
3098 inst.relax_inst = 0x8000;
3103 inst.relax_inst = 0x8000;
3107 else if ((inst.instruction & 0x3e000000) == 0x2c000000)
3110 if ((((inst.instruction >> 15) & 0x10) == 0) && (((inst.instruction >> 20) & 0x10) == 0))
3113 if ((inst.instruction & 0x7fff) == 0)
3115 inst.relax_inst |= (((inst.instruction >> 15) & 0xf) << 4)
3116 | (((inst.instruction >> 20) & 0xf) << 8);
3117 inst.relax_size = 2;
3120 else if ((((inst.instruction >> 15) & 0xf) == 2)
3121 && ((inst.instruction & 0x7fff) < 32))
3123 inst.relax_inst = 0x7003 | (((inst.instruction >> 20) & 0xf) << 8)
3124 | ((inst.instruction & 0x7fff) << 3);
3125 inst.relax_size = 2;
3129 inst.relax_inst = 0x8000;
3134 inst.relax_inst = 0x8000;
3138 else if ((inst.instruction & 0x3e000000) == 0x2e000000)
3141 if ((((inst.instruction >> 15) & 0x10) == 0) && (((inst.instruction >> 20) & 0x10) == 0))
3144 if ((inst.instruction & 0x7fff) == 0)
3146 inst.relax_inst |= (((inst.instruction >> 15) & 0xf) << 4)
3147 | (((inst.instruction >> 20) & 0xf) << 8);
3148 inst.relax_size = 2;
3151 else if ((((inst.instruction >> 15) & 0xf) == 2)
3152 && ((inst.instruction & 0x7fff) < 32))
3154 inst.relax_inst = 0x7007 | (((inst.instruction >> 20) & 0xf) << 8)
3155 | ((inst.instruction & 0x7fff) << 3);
3156 inst.relax_size = 2;
3160 inst.relax_inst = 0x8000;
3165 inst.relax_inst = 0x8000;
3170 inst.relax_inst = 0x8000;
3178 inst.reloc.pc_rel = 0;
3184 inst.error = BAD_ARGS;
3203 cache_op = (inst.instruction >> 20) & 0x1F;
3204 sprintf (inst.name, "cache %d", cache_op);
3223 inst.error = _("missing ]");
3239 inst.error = _("missing ]");
3249 inst.error = BAD_ARGS;
3310 inst.error = _("missing ]");
3318 inst.error = BAD_ARGS;
3346 inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 20)
3347 | (((inst.instruction >> 4) & 0xf) << 15);
3348 inst.relax_size = 4;
3353 inst.error = _("missing ]");
3358 inst.error = BAD_ARGS;
3394 ldst_func = inst.instruction & LDST16_RI_MASK;
3408 if ((inst.instruction & 0x7000) == N16_LIU)
3410 inst.relax_inst |= ((inst.instruction >> 8) & 0xf) << 20
3411 | ((inst.instruction & 0xff) << 1);
3413 else if (((inst.instruction & 0x7007) == N16_LHP)
3414 || ((inst.instruction & 0x7007) == N16_SHP))
3416 inst.relax_inst |= ((inst.instruction >> 8) & 0xf) << 20 | 2 << 15
3417 | (((inst.instruction >> 3) & 0x1f) << 1);
3419 else if (((inst.instruction & 0x7007) == N16_LWP)
3420 || ((inst.instruction & 0x7007) == N16_SWP))
3422 inst.relax_inst |= ((inst.instruction >> 8) & 0xf) << 20 | 2 << 15
3423 | (((inst.instruction >> 3) & 0x1f) << 2);
3425 else if (((inst.instruction & 0x7007) == N16_LBUP)
3426 || ((inst.instruction & 0x7007) == N16_SBP))
3428 inst.relax_inst |= ((inst.instruction >> 8) & 0xf) << 20 | 2 << 15
3429 | (((inst.instruction >> 3) & 0x1f));
3432 inst.relax_size = 4;
3451 inst.instruction &= ~(1 << 12);
3453 inst.instruction |= H_bit_mask << 7;
3465 if (!inst.error)
3466 inst.error = _("base register nums are over 3 bit");
3474 if (!inst.error)
3475 inst.error = _("missing ]");
3481 if ((inst.instruction & 0xf) == 0xa)
3485 inst.relax_inst |= ((((inst.instruction >> 8) & 0xf) | 0x10) << 20)
3486 | (((inst.instruction >> 4) & 0x7) << 15) | (4 << 3);
3490 inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 20)
3491 | (((inst.instruction >> 4) & 0x7) << 15) | (4 << 3);
3499 inst.relax_inst |= ((((inst.instruction >> 8) & 0xf) | 0x10) << 20)
3500 | (((inst.instruction >> 4) & 0x7) << 15) | (((-4) & 0xfff) << 3);
3504 inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 20)
3505 | (((inst.instruction >> 4) & 0x7) << 15) | (((-4) & 0xfff) << 3);
3508 inst.relax_size = 4;
3512 inst.error = BAD_ARGS;
3524 inst.error = ERR_FOR_SCORE5U_ATOMIC;
3543 inst.error = _("missing +");
3549 inst.error = _("missing ]");
3581 unsigned int ldst_func = inst.instruction & LDST_UNALIGN_MASK;
3594 inst.error = _("missing +");
3603 inst.error = _("missing ]");
3609 inst.error = BAD_ARGS;
3621 inst.error = ERR_FOR_SCORE5U_ATOMIC;
3649 inst.error = _("missing ]");
3656 inst.error = BAD_ARGS;
3753 inst.bwarn = -1;
3789 inst.reloc.type = BFD_RELOC_SCORE_CALL15;
3790 memcpy (&fix_insts[0], &inst, sizeof (struct score_it));
3796 inst.reloc.type = BFD_RELOC_SCORE_GOT15;
3797 memcpy (&var_insts[0], &inst, sizeof (struct score_it));
3802 memcpy (&var_insts[1], &inst, sizeof (struct score_it));
3821 memcpy (&fix_insts[0], &inst, sizeof (struct score_it));
3829 memcpy (&var_insts[0], &inst, sizeof (struct score_it));
3851 memcpy (&fix_insts[0], &inst, sizeof (struct score_it));
3864 memcpy (&var_insts[0], &inst, sizeof (struct score_it));
3876 memcpy (&fix_insts[0], &inst, sizeof (struct score_it));
3884 memcpy (&var_insts[0], &inst, sizeof (struct score_it));
3893 inst.bwarn = -1;
3934 if ((score_pic == NO_PIC) || (!inst.reloc.exp.X_add_symbol))
3946 assert (inst.reloc.exp.X_add_symbol);
3947 build_la_pic (reg_rd, inst.reloc.exp);
3951 inst.bwarn = -1;
3991 else if (inst.reloc.exp.X_add_symbol)
3993 inst.error = _("li rd label isn't correct instruction form");
4009 inst.bwarn = -1;
4036 inst.error = BAD_ARGS;
4043 if (strcmp (inst.name, "rem") == 0 || strcmp (inst.name, "remu") == 0)
4066 if (strcmp (inst.name, "rem") == 0)
4071 else if (strcmp (inst.name, "remu") == 0)
4078 sprintf (append_str, "%s r%d, r%d", inst.name, reg_rs1, reg_rs2);
4091 inst.bwarn = -1;
4108 memcpy (&inst_backup, &inst, sizeof (struct score_it));
4124 memcpy (&inst, &inst_backup, sizeof (struct score_it));
4214 memcpy (&fix_insts[0], &inst, sizeof (struct score_it));
4220 inst.reloc.type = BFD_RELOC_SCORE_GOT15;
4221 memcpy (&var_insts[0], &inst, sizeof (struct score_it));
4226 memcpy (&var_insts[1], &inst, sizeof (struct score_it));
4235 inst.bwarn = -1;
4239 inst.error = _("PIC code offset overflow (max 16 signed bits)");
4262 memcpy (&inst_backup, &inst, sizeof (struct score_it));
4278 inst.type = Rd_rvalueRs_preSI12;
4285 inst.type = Rd_rvalueRs_SI15;
4286 if ((my_get_expression (&inst.reloc.exp, &backup_str) == (int) FAIL)
4287 || (validate_immediate (inst.reloc.exp.X_add_number, _VALUE, 0) == (int) FAIL)
4294 if (inst.reloc.exp.X_add_symbol == 0)
4296 memcpy (&inst, &inst_backup, sizeof (struct score_it));
4303 inst.type = Rd_rvalueRs_SI15;
4312 if (inst.reloc.exp.X_add_symbol == 0)
4314 if (!inst.error)
4315 inst.error = BAD_ARGS;
4323 ldst_idx = inst.instruction & OPC_PSEUDOLDST_MASK;
4324 build_lwst_pic (reg_rd, inst.reloc.exp, score_ldst_insns[ldst_idx * 3 + 0].template);
4329 if ((inst.reloc.exp.X_add_number <= 0x3fff)
4330 && (inst.reloc.exp.X_add_number >= -0x4000)
4331 && (!nopic_need_relax (inst.reloc.exp.X_add_symbol, 1)))
4336 ldst_idx = inst.instruction & OPC_PSEUDOLDST_MASK;
4337 inst.instruction &= ~OPC_PSEUDOLDST_MASK;
4338 inst.instruction |= score_ldst_insns[ldst_idx * 3 + 0].value;
4339 inst.instruction |= reg_rd << 20;
4340 inst.instruction |= GP << 15;
4341 inst.relax_inst = 0x8000;
4342 inst.relax_size = 0;
4348 /* Backup inst. */
4349 memcpy (&inst_main, &inst, sizeof (struct score_it));
4366 memcpy (&inst_expand[i], &inst, sizeof (struct score_it));
4432 inst.bwarn = -1;
4443 || (my_get_expression (&inst.reloc.exp, &str) == (int) FAIL)
4450 if (inst.reloc.exp.X_add_symbol == 0)
4452 if (!inst.error)
4453 inst.error = BAD_ARGS;
4458 inst.instruction |= GP << 15;
4459 inst.reloc.type = BFD_RELOC_SCORE_GOT15;
4469 if (((inst.instruction & 0x3e0003ff) == 0x0c000004)
4470 || ((inst.instruction & 0x3e0003ff) == 0x0c000024)
4471 || ((inst.instruction & 0x3e0003ff) == 0x0c000044)
4472 || ((inst.instruction & 0x3e0003ff) == 0x0c000064))
4474 inst.error = ERR_FOR_SCORE5U_MMU;
4481 if (inst.relax_inst != 0x8000)
4483 if (inst.type == NO_OPD)
4485 inst.relax_size = 2;
4489 inst.relax_size = 4;
4500 if (my_get_expression (&inst.reloc.exp, &str) == (int) FAIL
4504 if (inst.reloc.exp.X_add_symbol == 0)
4506 inst.error = _("lacking label ");
4510 if (((inst.reloc.exp.X_add_number & 0xff000000) != 0)
4511 && ((inst.reloc.exp.X_add_number & 0xff000000) != 0xff000000))
4513 inst.error = _("invalid constant: 25 bit expression not in range -2^24..2^24");
4519 inst.reloc.type = BFD_RELOC_SCORE_JMP;
4520 inst.reloc.pc_rel = 1;
4528 if (my_get_expression (&inst.reloc.exp, &str) == (int) FAIL
4533 else if (inst.reloc.exp.X_add_symbol == 0)
4535 inst.error = _("lacking label ");
4538 else if (((inst.reloc.exp.X_add_number & 0xfffff800) != 0)
4539 && ((inst.reloc.exp.X_add_number & 0xfffff800) != 0xfffff800))
4541 inst.error = _("invalid constant: 12 bit expression not in range -2^11..2^11");
4545 inst.reloc.type = BFD_RELOC_SCORE16_JMP;
4546 inst.reloc.pc_rel = 1;
4554 if (my_get_expression (&inst.reloc.exp, &str) == (int) FAIL
4559 else if (inst.reloc.exp.X_add_symbol == 0)
4561 inst.error = _("lacking label ");
4564 else if (((inst.reloc.exp.X_add_number & 0xff000000) != 0)
4565 && ((inst.reloc.exp.X_add_number & 0xff000000) != 0xff000000))
4567 inst.error = _("invalid constant: 20 bit expression not in range -2^19..2^19");
4571 inst.reloc.type = BFD_RELOC_SCORE_BRANCH;
4572 inst.reloc.pc_rel = 1;
4575 inst.instruction |= (inst.reloc.exp.X_add_number & 0x3fe) | ((inst.reloc.exp.X_add_number & 0xffc00) << 5);
4578 if ((inst.relax_inst != 0x8000) && (abs_value & 0xfffffe00) == 0)
4580 inst.relax_inst |= (((inst.instruction >> 10) & 0xf) << 8);
4581 inst.relax_inst |= ((inst.reloc.exp.X_add_number >> 1) & 0xff);
4582 inst.relax_size = 2;
4586 inst.relax_inst = 0x8000;
4593 if ((my_get_expression (&inst.reloc.exp, &str) == (int) FAIL
4598 else if (inst.reloc.exp.X_add_symbol == 0)
4600 inst.error = _("lacking label");
4602 else if (((inst.reloc.exp.X_add_number & 0xffffff00) != 0)
4603 && ((inst.reloc.exp.X_add_number & 0xffffff00) != 0xffffff00))
4605 inst.error = _("invalid constant: 9 bit expression not in range -2^8..2^8");
4609 inst.reloc.type = BFD_RELOC_SCORE16_BRANCH;
4610 inst.reloc.pc_rel = 1;
4611 inst.instruction |= ((inst.reloc.exp.X_add_number >> 1) & 0xff);
5627 if (inst.error)
5630 memcpy (&pec_part_1, &inst, sizeof (inst));
5633 if (inst.error)
5636 if ( ((pec_part_1.size == INSN_SIZE) && (inst.size == INSN_SIZE))
5637 || ((pec_part_1.size == INSN_SIZE) && (inst.size == INSN16_SIZE))
5638 || ((pec_part_1.size == INSN16_SIZE) && (inst.size == INSN_SIZE)))
5640 inst.error = _("pce instruction error (16 bit || 16 bit)'");
5641 sprintf (inst.str, insnstr);
5645 if (!inst.error)
5646 gen_insn_frag (&pec_part_1, &inst);
5655 memset (&inst, '\0', sizeof (inst));
5661 if (inst.error)
5662 as_bad (_("%s -- `%s'"), inst.error, inst.str);
5673 if (inst.error == NULL)
5675 inst.error = _("bad expression");