Lines Matching refs:base
75 * Calculates the base, start & end and returns the same for a
118 * | base ptr |
141 void nlm_cms_setup_credits(uint64_t base, int destid, int srcid, int credit)
146 nlm_write_cms_reg(base, CMS_OUTPUTQ_CREDIT_CFG, val);
151 * base - CMS module base address for this node.
158 int nlm_cms_alloc_spill_q(uint64_t base, int qid, uint64_t spill_base,
168 queue_config = nlm_read_cms_reg(base,(CMS_OUTPUTQ_CONFIG(qid)));
177 nlm_write_cms_reg(base,(CMS_OUTPUTQ_CONFIG(qid)),queue_config);
182 uint64_t nlm_cms_get_onchip_queue (uint64_t base, int qid)
184 return nlm_read_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid));
187 void nlm_cms_set_onchip_queue (uint64_t base, int qid, uint64_t val)
191 rdval = nlm_read_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid));
193 nlm_write_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid), rdval);
196 void nlm_cms_per_queue_level_intr(uint64_t base, int qid, int sub_type,
201 val = nlm_read_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid));
208 nlm_write_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid), val);
211 void nlm_cms_per_queue_timer_intr(uint64_t base, int qid, int sub_type,
216 val = nlm_read_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid));
223 nlm_write_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid), val);
227 int nlm_cms_outputq_intr_check(uint64_t base, int qid)
230 val = nlm_read_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid));
235 void nlm_cms_outputq_clr_intr(uint64_t base, int qid)
238 val = nlm_read_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid));
240 nlm_write_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid), val);
243 void nlm_cms_illegal_dst_error_intr(uint64_t base, int en)
247 val = nlm_read_cms_reg(base, CMS_MSG_CONFIG);
249 nlm_write_cms_reg(base, CMS_MSG_CONFIG, val);
252 void nlm_cms_timeout_error_intr(uint64_t base, int en)
256 val = nlm_read_cms_reg(base, CMS_MSG_CONFIG);
258 nlm_write_cms_reg(base, CMS_MSG_CONFIG, val);
261 void nlm_cms_biu_error_resp_intr(uint64_t base, int en)
265 val = nlm_read_cms_reg(base, CMS_MSG_CONFIG);
267 nlm_write_cms_reg(base, CMS_MSG_CONFIG, val);
270 void nlm_cms_spill_uncorrectable_ecc_error_intr(uint64_t base, int en)
274 val = nlm_read_cms_reg(base, CMS_MSG_CONFIG);
276 nlm_write_cms_reg(base, CMS_MSG_CONFIG, val);
279 void nlm_cms_spill_correctable_ecc_error_intr(uint64_t base, int en)
283 val = nlm_read_cms_reg(base, CMS_MSG_CONFIG);
285 nlm_write_cms_reg(base, CMS_MSG_CONFIG, val);
288 void nlm_cms_outputq_uncorrectable_ecc_error_intr(uint64_t base, int en)
292 val = nlm_read_cms_reg(base, CMS_MSG_CONFIG);
294 nlm_write_cms_reg(base, CMS_MSG_CONFIG, val);
297 void nlm_cms_outputq_correctable_ecc_error_intr(uint64_t base, int en)
301 val = nlm_read_cms_reg(base, CMS_MSG_CONFIG);
303 nlm_write_cms_reg(base, CMS_MSG_CONFIG, val);
306 uint64_t nlm_cms_network_error_status(uint64_t base)
308 return nlm_read_cms_reg(base, CMS_MSG_ERR);
333 void nlm_cms_trace_setup(uint64_t base, int en, uint64_t trace_base,
340 nlm_write_cms_reg(base, CMS_TRACE_BASE_ADDR, trace_base);
341 nlm_write_cms_reg(base, CMS_TRACE_LIMIT_ADDR, trace_limit);
343 val = nlm_read_cms_reg(base, CMS_TRACE_CONFIG);
350 nlm_write_cms_reg(base, CMS_MSG_CONFIG, val);
353 void nlm_cms_endian_byte_swap (uint64_t base, int en)
355 nlm_write_cms_reg(base, CMS_MSG_ENDIAN_SWAP, en);