Lines Matching defs:pll
94 uint32_t pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv;
105 pll = ATH_READ_REG(AR934X_SRIF_CPU_DPLL2_REG);
106 if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
107 out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
109 pll = ATH_READ_REG(AR934X_SRIF_CPU_DPLL1_REG);
110 nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
112 nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
113 ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
117 pll = ATH_READ_REG(AR934X_PLL_CPU_CONFIG_REG);
118 out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
120 ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
122 nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
124 nfrac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
132 pll = ATH_READ_REG(AR934X_SRIF_DDR_DPLL2_REG);
133 if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
134 out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
136 pll = ATH_READ_REG(AR934X_SRIF_DDR_DPLL1_REG);
137 nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
139 nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
140 ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
144 pll = ATH_READ_REG(AR934X_PLL_DDR_CONFIG_REG);
145 out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
147 ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
149 nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
151 nfrac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
246 ar934x_chip_set_pll_ge(int unit, int speed, uint32_t pll)
251 ATH_WRITE_REG(AR934X_PLL_ETH_XMII_CONTROL_REG, pll);
292 uint32_t pll;
296 pll = AR934X_PLL_VAL_10;
299 pll = AR934X_PLL_VAL_100;
302 pll = AR934X_PLL_VAL_1000;
306 pll = 0;
308 return (pll);