Lines Matching refs:mac
164 static inline bool bwn_nphy_ipa(struct bwn_mac *mac)
166 bwn_band_t band = bwn_current_band(mac);
167 return ((mac->mac_phy.phy_n->ipa2g_on && band == BWN_BAND_2G) ||
168 (mac->mac_phy.phy_n->ipa5g_on && band == BWN_BAND_5G));
172 static uint8_t bwn_nphy_get_rx_core_state(struct bwn_mac *mac)
174 return (BWN_PHY_READ(mac, BWN_NPHY_RFSEQCA) & BWN_NPHY_RFSEQCA_RXEN) >>
183 static void bwn_nphy_force_rf_sequence(struct bwn_mac *mac,
195 uint16_t seq_mode = BWN_PHY_READ(mac, BWN_NPHY_RFSEQMODE);
198 BWN_WARNPRINTF(mac->mac_sc, "%s: seq %d > max", __func__, seq);
201 BWN_PHY_SET(mac, BWN_NPHY_RFSEQMODE,
203 BWN_PHY_SET(mac, BWN_NPHY_RFSEQTR, trigger[seq]);
205 if (!(BWN_PHY_READ(mac, BWN_NPHY_RFSEQST) & trigger[seq]))
209 BWN_ERRPRINTF(mac->mac_sc, "RF sequence status timeout\n");
211 BWN_PHY_WRITE(mac, BWN_NPHY_RFSEQMODE, seq_mode);
214 static void bwn_nphy_rf_ctl_override_rev19(struct bwn_mac *mac, uint16_t field,
222 static void bwn_nphy_rf_ctl_override_rev7(struct bwn_mac *mac, uint16_t field,
226 struct bwn_phy *phy = &mac->mac_phy;
237 BWN_WARNPRINTF(mac->mac_sc, "%s: phy rev %d out of range\n",
244 e = bwn_nphy_get_rf_ctl_over_rev7(mac, field, override);
248 BWN_ERRPRINTF(mac->mac_sc, "Invalid override value %d\n", override);
257 BWN_PHY_MASK(mac, en_addr, ~en_mask);
259 BWN_PHY_MASK(mac, val_addr, ~e->val_mask);
262 BWN_PHY_SET(mac, en_addr, en_mask);
264 BWN_PHY_SETMASK(mac, val_addr, ~e->val_mask, (value << e->val_shift));
271 static void bwn_nphy_rf_ctl_override_one_to_many(struct bwn_mac *mac,
275 struct bwn_phy *phy = &mac->mac_phy;
279 BWN_ERRPRINTF(mac->mac_sc, "%s: phy rev %d out of range\n",
286 bwn_nphy_rf_ctl_override_rev7(mac, 0x20, value, core, off, 1);
287 bwn_nphy_rf_ctl_override_rev7(mac, 0x10, value, core, off, 1);
288 bwn_nphy_rf_ctl_override_rev7(mac, 0x08, value, core, off, 1);
291 bwn_nphy_rf_ctl_override_rev7(mac, 0x4, value, core, off, 1);
292 bwn_nphy_rf_ctl_override_rev7(mac, 0x2, value, core, off, 1);
293 bwn_nphy_rf_ctl_override_rev7(mac, 0x1, value, core, off, 1);
294 bwn_nphy_rf_ctl_override_rev7(mac, 0x2, value, core, off, 2);
295 bwn_nphy_rf_ctl_override_rev7(mac, 0x0800, 0, core, off, 1);
298 bwn_nphy_rf_ctl_override_rev7(mac, 0x4, value, core, off, 0);
299 bwn_nphy_rf_ctl_override_rev7(mac, 0x2, value, core, off, 1);
300 bwn_nphy_rf_ctl_override_rev7(mac, 0x1, value, core, off, 2);
301 bwn_nphy_rf_ctl_override_rev7(mac, 0x0800, 1, core, off, 1);
305 bwn_nphy_rf_ctl_override_rev7(mac, 0x0800, tmp, core, off, 0);
307 bwn_nphy_rf_ctl_override_rev7(mac, 0x6000, tmp, core, off, 0);
311 bwn_nphy_rf_ctl_override_rev7(mac, 0x1000, tmp, core, off, 0);
313 bwn_nphy_rf_ctl_override_rev7(mac, 0x4000, tmp, core, off, 0);
319 static void bwn_nphy_rf_ctl_override(struct bwn_mac *mac, uint16_t field,
328 BWN_ERRPRINTF(mac->mac_sc, "%s: field 0x%04x has >1 bit set\n",
333 if (mac->mac_phy.rev >= 3) {
337 BWN_ERRPRINTF(mac->mac_sc,
349 BWN_PHY_MASK(mac, en_addr, ~(field));
350 BWN_PHY_MASK(mac, val_addr,
354 BWN_PHY_SET(mac, en_addr, field);
355 BWN_PHY_SETMASK(mac, val_addr,
364 BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_OVER, ~(field));
367 BWN_PHY_SET(mac, BWN_NPHY_RFCTL_OVER, field);
372 BWN_ERRPRINTF(mac->mac_sc,
387 BWN_PHY_SETMASK(mac, addr, ~(rf_ctrl->bmask),
390 BWN_PHY_SET(mac, BWN_NPHY_RFCTL_OVER, 0x1);
391 BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD,
394 BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_OVER, 0xFFFE);
399 static void bwn_nphy_rf_ctl_intc_override_rev7(struct bwn_mac *mac,
417 BWN_PHY_WRITE(mac, reg, 0);
418 BWN_PHY_MASK(mac, 0x2ff, ~0x2000);
419 bwn_nphy_force_rf_sequence(mac, BWN_RFSEQ_RESET2RX);
422 BWN_PHY_SETMASK(mac, reg, ~0xC0, value << 6);
423 BWN_PHY_SET(mac, reg, 0x400);
425 BWN_PHY_MASK(mac, 0x2ff, ~0xC000 & 0xFFFF);
426 BWN_PHY_SET(mac, 0x2ff, 0x2000);
427 BWN_PHY_SET(mac, 0x2ff, 0x0001);
431 if (bwn_current_band(mac) == BWN_BAND_5G)
435 BWN_PHY_SETMASK(mac, reg, ~tmp, val);
436 BWN_PHY_SET(mac, reg, 0x1000);
439 if (bwn_current_band(mac) == BWN_BAND_5G) {
448 BWN_PHY_SETMASK(mac, reg, ~tmp, val);
449 BWN_PHY_MASK(mac, reg, ~tmp2);
452 if (bwn_current_band(mac) == BWN_BAND_5G) {
461 BWN_PHY_SETMASK(mac, reg, ~tmp, val);
462 BWN_PHY_MASK(mac, reg, ~tmp2);
469 static void bwn_nphy_rf_ctl_intc_override(struct bwn_mac *mac,
476 if (mac->mac_phy.rev >= 7) {
477 bwn_nphy_rf_ctl_intc_override_rev7(mac, intc_override, value,
482 if (mac->mac_phy.rev < 3) {
483 BWN_ERRPRINTF(mac->mac_sc, "%s: phy rev %d out of range\n",
485 mac->mac_phy.rev);
494 BWN_PHY_SET(mac, reg, 0x400);
498 BWN_PHY_WRITE(mac, reg, 0);
499 bwn_nphy_force_rf_sequence(mac, BWN_RFSEQ_RESET2RX);
503 BWN_PHY_SETMASK(mac, BWN_NPHY_RFCTL_INTC1,
505 BWN_PHY_SETMASK(mac, BWN_NPHY_TXF_40CO_B1S1,
507 BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD,
510 if (!(BWN_PHY_READ(mac, BWN_NPHY_RFCTL_CMD) & BWN_NPHY_RFCTL_CMD_START)) {
517 BWN_ERRPRINTF(mac->mac_sc,
519 BWN_PHY_MASK(mac, BWN_NPHY_TXF_40CO_B1S1,
522 BWN_PHY_SETMASK(mac, BWN_NPHY_RFCTL_INTC2,
524 BWN_PHY_SETMASK(mac, BWN_NPHY_RFCTL_OVER,
526 BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD,
529 if (!(BWN_PHY_READ(mac, BWN_NPHY_RFCTL_CMD) & BWN_NPHY_RFCTL_CMD_RXTX)) {
536 BWN_ERRPRINTF(mac->mac_sc,
538 BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_OVER,
543 if (bwn_current_band(mac) == BWN_BAND_5G) {
550 BWN_PHY_SETMASK(mac, reg, ~tmp, val);
553 if (bwn_current_band(mac) == BWN_BAND_5G) {
560 BWN_PHY_SETMASK(mac, reg, ~tmp, val);
563 if (bwn_current_band(mac) == BWN_BAND_5G) {
570 BWN_PHY_SETMASK(mac, reg, ~tmp, val);
581 static void bwn_nphy_write_clip_detection(struct bwn_mac *mac,
584 BWN_PHY_WRITE(mac, BWN_NPHY_C1_CLIP1THRES, clip_st[0]);
585 BWN_PHY_WRITE(mac, BWN_NPHY_C2_CLIP1THRES, clip_st[1]);
589 static void bwn_nphy_read_clip_detection(struct bwn_mac *mac, uint16_t *clip_st)
591 clip_st[0] = BWN_PHY_READ(mac, BWN_NPHY_C1_CLIP1THRES);
592 clip_st[1] = BWN_PHY_READ(mac, BWN_NPHY_C2_CLIP1THRES);
596 static uint16_t bwn_nphy_classifier(struct bwn_mac *mac, uint16_t mask, uint16_t val)
598 struct bwn_softc *sc = mac->mac_sc;
602 bwn_mac_suspend(mac);
604 tmp = BWN_PHY_READ(mac, BWN_NPHY_CLASSCTL);
609 BWN_PHY_SETMASK(mac, BWN_NPHY_CLASSCTL, 0xFFF8, tmp);
612 bwn_mac_enable(mac);
618 static void bwn_nphy_reset_cca(struct bwn_mac *mac)
622 bwn_phy_force_clock(mac, 1);
623 bbcfg = BWN_PHY_READ(mac, BWN_NPHY_BBCFG);
624 BWN_PHY_WRITE(mac, BWN_NPHY_BBCFG, bbcfg | BWN_NPHY_BBCFG_RSTCCA);
626 BWN_PHY_WRITE(mac, BWN_NPHY_BBCFG, bbcfg & ~BWN_NPHY_BBCFG_RSTCCA);
627 bwn_phy_force_clock(mac, 0);
628 bwn_nphy_force_rf_sequence(mac, BWN_RFSEQ_RESET2RX);
632 static void bwn_nphy_stay_in_carrier_search(struct bwn_mac *mac, bool enable)
634 struct bwn_phy *phy = &mac->mac_phy;
640 nphy->classifier_state = bwn_nphy_classifier(mac, 0, 0);
641 bwn_nphy_classifier(mac, 0x7,
643 bwn_nphy_read_clip_detection(mac, nphy->clip_state);
644 bwn_nphy_write_clip_detection(mac, clip);
646 bwn_nphy_reset_cca(mac);
649 bwn_nphy_classifier(mac, 0x7, nphy->classifier_state);
650 bwn_nphy_write_clip_detection(mac, nphy->clip_state);
656 static uint16_t bwn_nphy_read_lpf_ctl(struct bwn_mac *mac, uint16_t offset)
659 offset = bwn_is_40mhz(mac) ? 0x159 : 0x154;
660 return bwn_ntab_read(mac, BWN_NTAB16(7, offset)) & 0x7;
664 static void bwn_nphy_adjust_lna_gain_table(struct bwn_mac *mac)
666 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
676 bwn_nphy_stay_in_carrier_search(mac, 1);
679 if (bwn_current_band(mac) == BWN_BAND_2G) {
683 tmp = 40370 - 315 * bwn_get_chan(mac);
685 tmp = 23242 - 224 * bwn_get_chan(mac);
705 bwn_ntab_write_bulk(mac, BWN_NTAB16(i, 8), 4, data);
710 BWN_PHY_SETMASK(mac, BWN_NPHY_C1_MINMAX_GAIN, ~BWN_NPHY_C1_MINGAIN,
712 BWN_PHY_SETMASK(mac, BWN_NPHY_C2_MINMAX_GAIN, ~BWN_NPHY_C2_MINGAIN,
716 bwn_nphy_stay_in_carrier_search(mac, 0);
720 static void bwn_nphy_set_rf_sequence(struct bwn_mac *mac, uint8_t cmd,
723 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
725 uint8_t end = (mac->mac_phy.rev >= 3) ? 0x1F : 0x0F;
730 bwn_nphy_stay_in_carrier_search(mac, true);
732 bwn_ntab_write_bulk(mac, BWN_NTAB8(7, offset1), length, events);
733 bwn_ntab_write_bulk(mac, BWN_NTAB8(7, offset2), length, delays);
736 bwn_ntab_write(mac, BWN_NTAB8(7, offset1 + i), end);
737 bwn_ntab_write(mac, BWN_NTAB8(7, offset2 + i), 1);
741 bwn_nphy_stay_in_carrier_search(mac, false);
748 static void bwn_radio_2057_chantab_upload(struct bwn_mac *mac,
753 BWN_RF_WRITE(mac, R2057_VCOCAL_COUNTVAL0, e_r7_2g->radio_vcocal_countval0);
754 BWN_RF_WRITE(mac, R2057_VCOCAL_COUNTVAL1, e_r7_2g->radio_vcocal_countval1);
755 BWN_RF_WRITE(mac, R2057_RFPLL_REFMASTER_SPAREXTALSIZE, e_r7_2g->radio_rfpll_refmaster_sparextalsize);
756 BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_R1, e_r7_2g->radio_rfpll_loopfilter_r1);
757 BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_C2, e_r7_2g->radio_rfpll_loopfilter_c2);
758 BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_C1, e_r7_2g->radio_rfpll_loopfilter_c1);
759 BWN_RF_WRITE(mac, R2057_CP_KPD_IDAC, e_r7_2g->radio_cp_kpd_idac);
760 BWN_RF_WRITE(mac, R2057_RFPLL_MMD0, e_r7_2g->radio_rfpll_mmd0);
761 BWN_RF_WRITE(mac, R2057_RFPLL_MMD1, e_r7_2g->radio_rfpll_mmd1);
762 BWN_RF_WRITE(mac, R2057_VCOBUF_TUNE, e_r7_2g->radio_vcobuf_tune);
763 BWN_RF_WRITE(mac, R2057_LOGEN_MX2G_TUNE, e_r7_2g->radio_logen_mx2g_tune);
764 BWN_RF_WRITE(mac, R2057_LOGEN_INDBUF2G_TUNE, e_r7_2g->radio_logen_indbuf2g_tune);
765 BWN_RF_WRITE(mac, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, e_r7_2g->radio_txmix2g_tune_boost_pu_core0);
766 BWN_RF_WRITE(mac, R2057_PAD2G_TUNE_PUS_CORE0, e_r7_2g->radio_pad2g_tune_pus_core0);
767 BWN_RF_WRITE(mac, R2057_LNA2G_TUNE_CORE0, e_r7_2g->radio_lna2g_tune_core0);
768 BWN_RF_WRITE(mac, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1, e_r7_2g->radio_txmix2g_tune_boost_pu_core1);
769 BWN_RF_WRITE(mac, R2057_PAD2G_TUNE_PUS_CORE1, e_r7_2g->radio_pad2g_tune_pus_core1);
770 BWN_RF_WRITE(mac, R2057_LNA2G_TUNE_CORE1, e_r7_2g->radio_lna2g_tune_core1);
773 BWN_RF_WRITE(mac, R2057_VCOCAL_COUNTVAL0, e_r7->radio_vcocal_countval0);
774 BWN_RF_WRITE(mac, R2057_VCOCAL_COUNTVAL1, e_r7->radio_vcocal_countval1);
775 BWN_RF_WRITE(mac, R2057_RFPLL_REFMASTER_SPAREXTALSIZE, e_r7->radio_rfpll_refmaster_sparextalsize);
776 BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_R1, e_r7->radio_rfpll_loopfilter_r1);
777 BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_C2, e_r7->radio_rfpll_loopfilter_c2);
778 BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_C1, e_r7->radio_rfpll_loopfilter_c1);
779 BWN_RF_WRITE(mac, R2057_CP_KPD_IDAC, e_r7->radio_cp_kpd_idac);
780 BWN_RF_WRITE(mac, R2057_RFPLL_MMD0, e_r7->radio_rfpll_mmd0);
781 BWN_RF_WRITE(mac, R2057_RFPLL_MMD1, e_r7->radio_rfpll_mmd1);
782 BWN_RF_WRITE(mac, R2057_VCOBUF_TUNE, e_r7->radio_vcobuf_tune);
783 BWN_RF_WRITE(mac, R2057_LOGEN_MX2G_TUNE, e_r7->radio_logen_mx2g_tune);
784 BWN_RF_WRITE(mac, R2057_LOGEN_MX5G_TUNE, e_r7->radio_logen_mx5g_tune);
785 BWN_RF_WRITE(mac, R2057_LOGEN_INDBUF2G_TUNE, e_r7->radio_logen_indbuf2g_tune);
786 BWN_RF_WRITE(mac, R2057_LOGEN_INDBUF5G_TUNE, e_r7->radio_logen_indbuf5g_tune);
787 BWN_RF_WRITE(mac, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, e_r7->radio_txmix2g_tune_boost_pu_core0);
788 BWN_RF_WRITE(mac, R2057_PAD2G_TUNE_PUS_CORE0, e_r7->radio_pad2g_tune_pus_core0);
789 BWN_RF_WRITE(mac, R2057_PGA_BOOST_TUNE_CORE0, e_r7->radio_pga_boost_tune_core0);
790 BWN_RF_WRITE(mac, R2057_TXMIX5G_BOOST_TUNE_CORE0, e_r7->radio_txmix5g_boost_tune_core0);
791 BWN_RF_WRITE(mac, R2057_PAD5G_TUNE_MISC_PUS_CORE0, e_r7->radio_pad5g_tune_misc_pus_core0);
792 BWN_RF_WRITE(mac, R2057_LNA2G_TUNE_CORE0, e_r7->radio_lna2g_tune_core0);
793 BWN_RF_WRITE(mac, R2057_LNA5G_TUNE_CORE0, e_r7->radio_lna5g_tune_core0);
794 BWN_RF_WRITE(mac, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1, e_r7->radio_txmix2g_tune_boost_pu_core1);
795 BWN_RF_WRITE(mac, R2057_PAD2G_TUNE_PUS_CORE1, e_r7->radio_pad2g_tune_pus_core1);
796 BWN_RF_WRITE(mac, R2057_PGA_BOOST_TUNE_CORE1, e_r7->radio_pga_boost_tune_core1);
797 BWN_RF_WRITE(mac, R2057_TXMIX5G_BOOST_TUNE_CORE1, e_r7->radio_txmix5g_boost_tune_core1);
798 BWN_RF_WRITE(mac, R2057_PAD5G_TUNE_MISC_PUS_CORE1, e_r7->radio_pad5g_tune_misc_pus_core1);
799 BWN_RF_WRITE(mac, R2057_LNA2G_TUNE_CORE1, e_r7->radio_lna2g_tune_core1);
800 BWN_RF_WRITE(mac, R2057_LNA5G_TUNE_CORE1, e_r7->radio_lna5g_tune_core1);
804 static void bwn_radio_2057_setup(struct bwn_mac *mac,
808 struct bwn_phy *phy = &mac->mac_phy;
810 bwn_radio_2057_chantab_upload(mac, tabent_r7, tabent_r7_2g);
815 if (bwn_current_band(mac) == BWN_BAND_2G) {
816 BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_R1, 0x3f);
817 BWN_RF_WRITE(mac, R2057_CP_KPD_IDAC, 0x3f);
818 BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_C1, 0x8);
819 BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_C2, 0x8);
821 BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_R1, 0x1f);
822 BWN_RF_WRITE(mac, R2057_CP_KPD_IDAC, 0x3f);
823 BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_C1, 0x8);
824 BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_C2, 0x8);
828 BWN_RF_WRITE(mac, R2057_LOGEN_PTAT_RESETS, 0x20);
829 BWN_RF_WRITE(mac, R2057_VCOBUF_IDACS, 0x18);
830 if (bwn_current_band(mac) == BWN_BAND_5G) {
831 BWN_RF_WRITE(mac, R2057_LOGEN_PTAT_RESETS, 0x38);
832 BWN_RF_WRITE(mac, R2057_VCOBUF_IDACS, 0x0f);
834 if (bwn_is_40mhz(mac)) {
837 BWN_RF_WRITE(mac,
840 BWN_RF_WRITE(mac,
847 BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_R1, 0x1b);
848 BWN_RF_WRITE(mac, R2057_CP_KPD_IDAC, 0x3f);
849 BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_C1, 0x1f);
850 BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_C2, 0x1f);
854 if (bwn_current_band(mac) == BWN_BAND_2G) {
858 if (bwn_nphy_ipa(mac)) {
872 BWN_RF_WRITE(mac, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0,
875 BWN_RF_WRITE(mac, R2057_PAD2G_TUNE_PUS_CORE0,
878 BWN_RF_WRITE(mac, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1,
881 BWN_RF_WRITE(mac, R2057_PAD2G_TUNE_PUS_CORE1,
889 BWN_RF_MASK(mac, R2057_RFPLL_MISC_EN, ~0x01);
890 BWN_RF_MASK(mac, R2057_RFPLL_MISC_CAL_RESETN, ~0x04);
891 BWN_RF_SET(mac, R2057_RFPLL_MISC_CAL_RESETN, 0x4);
892 BWN_RF_SET(mac, R2057_RFPLL_MISC_EN, 0x01);
900 static uint8_t bwn_radio_2057_rcal(struct bwn_mac *mac)
902 struct bwn_phy *phy = &mac->mac_phy;
924 saved_regs_phy[i] = BWN_PHY_READ(mac, phy_to_store[i]);
926 saved_regs_phy_rf[i] = BWN_PHY_READ(mac, phy_to_store_rf[i]);
930 BWN_PHY_WRITE(mac, phy_to_store[i], 0);
931 BWN_PHY_WRITE(mac, BWN_NPHY_REV3_RFCTL_OVER0, 0x07ff);
932 BWN_PHY_WRITE(mac, BWN_NPHY_REV3_RFCTL_OVER1, 0x07ff);
933 BWN_PHY_WRITE(mac, BWN_NPHY_REV7_RF_CTL_OVER3, 0x07ff);
934 BWN_PHY_WRITE(mac, BWN_NPHY_REV7_RF_CTL_OVER4, 0x07ff);
935 BWN_PHY_WRITE(mac, BWN_NPHY_REV7_RF_CTL_OVER5, 0x007f);
936 BWN_PHY_WRITE(mac, BWN_NPHY_REV7_RF_CTL_OVER6, 0x007f);
940 BWN_PHY_MASK(mac, BWN_NPHY_REV7_RF_CTL_OVER3, ~0x2);
942 BWN_RF_SET(mac, R2057_IQTEST_SEL_PU, 0x1);
943 BWN_RF_SETMASK(mac, R2057v7_IQTEST_SEL_PU2, ~0x2, 0x1);
946 BWN_PHY_SET(mac, BWN_NPHY_REV7_RF_CTL_OVER3, 0x2);
947 BWN_PHY_SET(mac, BWN_NPHY_REV7_RF_CTL_MISC_REG3, 0x2);
948 saved_regs_radio[0] = BWN_RF_READ(mac, R2057_IQTEST_SEL_PU);
949 BWN_RF_WRITE(mac, R2057_IQTEST_SEL_PU, 0x11);
952 saved_regs_radio[0] = BWN_RF_READ(mac, R2057_IQTEST_SEL_PU);
953 saved_regs_radio[1] = BWN_RF_READ(mac, R2057v7_IQTEST_SEL_PU2);
954 BWN_PHY_SET(mac, BWN_NPHY_REV7_RF_CTL_MISC_REG3, 0x2);
955 BWN_PHY_SET(mac, BWN_NPHY_REV7_RF_CTL_OVER3, 0x2);
956 BWN_RF_WRITE(mac, R2057v7_IQTEST_SEL_PU2, 0x2);
957 BWN_RF_WRITE(mac, R2057_IQTEST_SEL_PU, 0x1);
962 BWN_RF_SET(mac, R2057_RCAL_CONFIG, 0x1);
966 BWN_RF_SET(mac, R2057_RCAL_CONFIG, 0x2);
971 BWN_RF_MASK(mac, R2057_RCAL_CONFIG, ~0x2);
974 if (!bwn_radio_wait_value(mac, R2057_RCAL_STATUS, 1, 1, 100, 1000000)) {
975 BWN_ERRPRINTF(mac->mac_sc, "Radio 0x2057 rcal timeout\n");
978 tmp = BWN_RF_READ(mac, R2057_RCAL_STATUS) & 0x3E;
981 BWN_RF_MASK(mac, R2057_RCAL_CONFIG, ~0x1);
985 BWN_PHY_WRITE(mac, phy_to_store_rf[i], saved_regs_phy_rf[i]);
987 BWN_PHY_WRITE(mac, phy_to_store[i], saved_regs_phy[i]);
992 BWN_RF_SETMASK(mac, R2057_TEMPSENSE_CONFIG, ~0x3C, tmp);
993 BWN_RF_SETMASK(mac, R2057_BANDGAP_RCAL_TRIM, ~0xF0,
997 BWN_RF_MASK(mac, R2057_IPA2G_CASCONV_CORE0, ~0x1);
998 BWN_RF_MASK(mac, R2057v7_IQTEST_SEL_PU2, ~0x2);
1001 BWN_RF_WRITE(mac, R2057_IQTEST_SEL_PU, saved_regs_radio[0]);
1004 BWN_RF_WRITE(mac, R2057_IQTEST_SEL_PU, saved_regs_radio[0]);
1005 BWN_RF_WRITE(mac, R2057v7_IQTEST_SEL_PU2, saved_regs_radio[1]);
1015 static uint16_t bwn_radio_2057_rccal(struct bwn_mac *mac)
1017 struct bwn_phy *phy = &mac->mac_phy;
1024 BWN_RF_WRITE(mac, R2057_RCCAL_MASTER, 0x61);
1025 BWN_RF_WRITE(mac, R2057_RCCAL_TRC0, 0xC0);
1027 BWN_RF_WRITE(mac, R2057v7_RCCAL_MASTER, 0x61);
1028 BWN_RF_WRITE(mac, R2057_RCCAL_TRC0, 0xE9);
1030 BWN_RF_WRITE(mac, R2057_RCCAL_X1, 0x6E);
1033 BWN_RF_WRITE(mac, R2057_RCCAL_START_R1_Q1_P1, 0x55);
1034 if (!bwn_radio_wait_value(mac, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500,
1036 BWN_DBGPRINTF(mac, "Radio 0x2057 rccal timeout\n");
1039 BWN_RF_WRITE(mac, R2057_RCCAL_START_R1_Q1_P1, 0x15);
1045 BWN_RF_WRITE(mac, R2057_RCCAL_MASTER, 0x69);
1046 BWN_RF_WRITE(mac, R2057_RCCAL_TRC0, 0xB0);
1048 BWN_RF_WRITE(mac, R2057v7_RCCAL_MASTER, 0x69);
1049 BWN_RF_WRITE(mac, R2057_RCCAL_TRC0, 0xD5);
1051 BWN_RF_WRITE(mac, R2057_RCCAL_X1, 0x6E);
1056 BWN_RF_WRITE(mac, R2057_RCCAL_START_R1_Q1_P1, 0x55);
1059 if (!bwn_radio_wait_value(mac, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500,
1061 BWN_DBGPRINTF(mac, "Radio 0x2057 rccal timeout\n");
1064 BWN_RF_WRITE(mac, R2057_RCCAL_START_R1_Q1_P1, 0x15);
1070 BWN_RF_WRITE(mac, R2057_RCCAL_MASTER, 0x73);
1071 BWN_RF_WRITE(mac, R2057_RCCAL_X1, 0x28);
1072 BWN_RF_WRITE(mac, R2057_RCCAL_TRC0, 0xB0);
1074 BWN_RF_WRITE(mac, R2057v7_RCCAL_MASTER, 0x73);
1075 BWN_RF_WRITE(mac, R2057_RCCAL_X1, 0x6E);
1076 BWN_RF_WRITE(mac, R2057_RCCAL_TRC0, 0x99);
1082 BWN_RF_WRITE(mac, R2057_RCCAL_START_R1_Q1_P1, 0x55);
1085 if (!bwn_radio_wait_value(mac, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500,
1087 BWN_ERRPRINTF(mac->mac_sc, "Radio 0x2057 rcal timeout\n");
1090 tmp = BWN_RF_READ(mac, R2057_RCCAL_DONE_OSCCAP);
1093 BWN_RF_WRITE(mac, R2057_RCCAL_START_R1_Q1_P1, 0x15);
1098 BWN_RF_MASK(mac, R2057_RCCAL_MASTER, ~0x1);
1100 BWN_RF_MASK(mac, R2057v7_RCCAL_MASTER, ~0x1);
1105 static void bwn_radio_2057_init_pre(struct bwn_mac *mac)
1107 BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_CMD, ~BWN_NPHY_RFCTL_CMD_CHIP0PU);
1109 BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_CMD, BWN_NPHY_RFCTL_CMD_OEPORFORCE);
1110 BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD, ~BWN_NPHY_RFCTL_CMD_OEPORFORCE);
1111 BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD, BWN_NPHY_RFCTL_CMD_CHIP0PU);
1114 static void bwn_radio_2057_init_post(struct bwn_mac *mac)
1116 BWN_RF_SET(mac, R2057_XTALPUOVR_PINCTRL, 0x1);
1119 BWN_RF_SET(mac, R2057_XTALPUOVR_PINCTRL, 0x2);
1121 BWN_RF_SET(mac, R2057_RFPLL_MISC_CAL_RESETN, 0x78);
1122 BWN_RF_SET(mac, R2057_XTAL_CONFIG2, 0x80);
1124 BWN_RF_MASK(mac, R2057_RFPLL_MISC_CAL_RESETN, ~0x78);
1125 BWN_RF_MASK(mac, R2057_XTAL_CONFIG2, ~0x80);
1127 if (mac->mac_phy.phy_do_full_init) {
1128 bwn_radio_2057_rcal(mac);
1129 bwn_radio_2057_rccal(mac);
1131 BWN_RF_MASK(mac, R2057_RFPLL_MASTER, ~0x8);
1135 static void bwn_radio_2057_init(struct bwn_mac *mac)
1137 bwn_radio_2057_init_pre(mac);
1138 r2057_upload_inittabs(mac);
1139 bwn_radio_2057_init_post(mac);
1146 static void bwn_chantab_radio_2056_upload(struct bwn_mac *mac,
1149 BWN_RF_WRITE(mac, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
1150 BWN_RF_WRITE(mac, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
1151 BWN_RF_WRITE(mac, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
1152 BWN_RF_WRITE(mac, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
1153 BWN_RF_WRITE(mac, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
1154 BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER1,
1156 BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER2,
1158 BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER3,
1160 BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER4,
1162 BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER5,
1164 BWN_RF_WRITE(mac, B2056_SYN_RESERVED_ADDR27,
1166 BWN_RF_WRITE(mac, B2056_SYN_RESERVED_ADDR28,
1168 BWN_RF_WRITE(mac, B2056_SYN_RESERVED_ADDR29,
1170 BWN_RF_WRITE(mac, B2056_SYN_LOGEN_VCOBUF1,
1172 BWN_RF_WRITE(mac, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
1173 BWN_RF_WRITE(mac, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
1174 BWN_RF_WRITE(mac, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
1176 BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_LNAA_TUNE,
1178 BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_LNAG_TUNE,
1181 BWN_RF_WRITE(mac, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
1183 BWN_RF_WRITE(mac, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
1185 BWN_RF_WRITE(mac, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
1187 BWN_RF_WRITE(mac, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
1189 BWN_RF_WRITE(mac, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
1191 BWN_RF_WRITE(mac, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
1193 BWN_RF_WRITE(mac, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
1195 BWN_RF_WRITE(mac, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
1198 BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_LNAA_TUNE,
1200 BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_LNAG_TUNE,
1203 BWN_RF_WRITE(mac, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
1205 BWN_RF_WRITE(mac, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
1207 BWN_RF_WRITE(mac, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
1209 BWN_RF_WRITE(mac, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
1211 BWN_RF_WRITE(mac, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
1213 BWN_RF_WRITE(mac, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
1215 BWN_RF_WRITE(mac, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
1217 BWN_RF_WRITE(mac, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
1222 static void bwn_radio_2056_setup(struct bwn_mac *mac,
1225 struct bwn_softc *sc = mac->mac_sc;
1226 bwn_band_t band = bwn_current_band(mac);
1234 DPRINTF(mac->mac_sc, BWN_DEBUG_RF, "%s: called\n", __func__);
1236 if (mac->mac_phy.rev < 3) {
1237 BWN_ERRPRINTF(mac->mac_sc, "%s: phy rev %d out of range\n",
1239 mac->mac_phy.rev);
1248 bwn_chantab_radio_2056_upload(mac, e);
1249 b2056_upload_syn_pll_cp2(mac, band == BWN_BAND_5G);
1252 bwn_current_band(mac) == BWN_BAND_2G) {
1253 BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
1254 BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
1257 BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER4, 0x14);
1258 BWN_RF_WRITE(mac, B2056_SYN_PLL_CP2, 0);
1260 BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER4, 0x0B);
1261 BWN_RF_WRITE(mac, B2056_SYN_PLL_CP2, 0x14);
1265 bwn_current_band(mac) == BWN_BAND_2G) {
1266 BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER1, 0x1f);
1267 BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER2, 0x1f);
1268 BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER4, 0x0b);
1269 BWN_RF_WRITE(mac, B2056_SYN_PLL_CP2, 0x20);
1272 bwn_current_band(mac) == BWN_BAND_5G) {
1273 BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
1274 BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
1275 BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER4, 0x05);
1276 BWN_RF_WRITE(mac, B2056_SYN_PLL_CP2, 0x0C);
1279 if (mac->mac_phy.phy_n->ipa2g_on && band == BWN_BAND_2G) {
1282 if (mac->mac_phy.rev >= 5) {
1283 BWN_RF_WRITE(mac,
1306 BWN_RF_WRITE(mac,
1309 BWN_RF_WRITE(mac,
1312 BWN_RF_WRITE(mac,
1315 BWN_RF_WRITE(mac,
1318 BWN_RF_WRITE(mac,
1321 BWN_RF_WRITE(mac,
1324 BWN_RF_WRITE(mac,
1328 bias = bwn_is_40mhz(mac) ? 0x40 : 0x20;
1329 BWN_RF_WRITE(mac,
1332 BWN_RF_WRITE(mac,
1335 BWN_RF_WRITE(mac,
1339 BWN_RF_WRITE(mac, offset | B2056_TX_PA_SPARE1, 0xee);
1341 } else if (mac->mac_phy.phy_n->ipa5g_on && band == BWN_BAND_5G) {
1342 uint16_t freq = bwn_get_centre_freq(mac);
1374 BWN_RF_WRITE(mac,
1376 BWN_RF_WRITE(mac,
1378 BWN_RF_WRITE(mac,
1380 BWN_RF_WRITE(mac,
1382 BWN_RF_WRITE(mac,
1384 BWN_RF_WRITE(mac,
1386 BWN_RF_WRITE(mac,
1388 BWN_RF_WRITE(mac,
1390 BWN_RF_WRITE(mac,
1392 BWN_RF_WRITE(mac,
1399 BWN_RF_WRITE(mac, B2056_SYN_PLL_VCOCAL12, 0x00);
1400 BWN_RF_WRITE(mac, B2056_TX_INTPAA_PA_MISC, 0x38);
1401 BWN_RF_WRITE(mac, B2056_TX_INTPAA_PA_MISC, 0x18);
1402 BWN_RF_WRITE(mac, B2056_TX_INTPAA_PA_MISC, 0x38);
1403 BWN_RF_WRITE(mac, B2056_TX_INTPAA_PA_MISC, 0x39);
1407 static uint8_t bwn_radio_2056_rcal(struct bwn_mac *mac)
1409 struct bwn_phy *phy = &mac->mac_phy;
1414 DPRINTF(mac->mac_sc, BWN_DEBUG_RF, "%s: called\n", __func__);
1416 mast2 = BWN_RF_READ(mac, B2056_SYN_PLL_MAST2);
1417 BWN_RF_WRITE(mac, B2056_SYN_PLL_MAST2, mast2 | 0x7);
1420 BWN_RF_WRITE(mac, B2056_SYN_RCAL_MASTER, 0x01);
1422 BWN_RF_WRITE(mac, B2056_SYN_RCAL_MASTER, 0x09);
1424 if (!bwn_radio_wait_value(mac, B2056_SYN_RCAL_CODE_OUT, 0x80, 0x80, 100,
1426 BWN_ERRPRINTF(mac->mac_sc, "Radio recalibration timeout\n");
1430 BWN_RF_WRITE(mac, B2056_SYN_RCAL_MASTER, 0x01);
1431 tmp = BWN_RF_READ(mac, B2056_SYN_RCAL_CODE_OUT);
1432 BWN_RF_WRITE(mac, B2056_SYN_RCAL_MASTER, 0x00);
1434 BWN_RF_WRITE(mac, B2056_SYN_PLL_MAST2, mast2);
1439 static void bwn_radio_init2056_pre(struct bwn_mac *mac)
1441 DPRINTF(mac->mac_sc, BWN_DEBUG_RF, "%s: called\n", __func__);
1443 BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_CMD,
1446 BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_CMD,
1448 BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD,
1450 BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD,
1454 static void bwn_radio_init2056_post(struct bwn_mac *mac)
1456 DPRINTF(mac->mac_sc, BWN_DEBUG_RF, "%s: called\n", __func__);
1458 BWN_RF_SET(mac, B2056_SYN_COM_CTRL, 0xB);
1459 BWN_RF_SET(mac, B2056_SYN_COM_PU, 0x2);
1460 BWN_RF_SET(mac, B2056_SYN_COM_RESET, 0x2);
1462 BWN_RF_MASK(mac, B2056_SYN_COM_RESET, ~0x2);
1463 BWN_RF_MASK(mac, B2056_SYN_PLL_MAST2, ~0xFC);
1464 BWN_RF_MASK(mac, B2056_SYN_RCCAL_CTRL0, ~0x1);
1465 if (mac->mac_phy.phy_do_full_init)
1466 bwn_radio_2056_rcal(mac);
1473 static void bwn_radio_init2056(struct bwn_mac *mac)
1475 DPRINTF(mac->mac_sc, BWN_DEBUG_RF, "%s: called\n", __func__);
1477 bwn_radio_init2056_pre(mac);
1478 b2056_upload_inittabs(mac, 0, 0);
1479 bwn_radio_init2056_post(mac);
1486 static void bwn_chantab_radio_upload(struct bwn_mac *mac,
1489 BWN_RF_WRITE(mac, B2055_PLL_REF, e->radio_pll_ref);
1490 BWN_RF_WRITE(mac, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
1491 BWN_RF_WRITE(mac, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
1492 BWN_RF_WRITE(mac, B2055_VCO_CAPTAIL, e->radio_vco_captail);
1493 BWN_READ_4(mac, BWN_MACCTL); /* flush writes */
1495 BWN_RF_WRITE(mac, B2055_VCO_CAL1, e->radio_vco_cal1);
1496 BWN_RF_WRITE(mac, B2055_VCO_CAL2, e->radio_vco_cal2);
1497 BWN_RF_WRITE(mac, B2055_PLL_LFC1, e->radio_pll_lfc1);
1498 BWN_RF_WRITE(mac, B2055_PLL_LFR1, e->radio_pll_lfr1);
1499 BWN_READ_4(mac, BWN_MACCTL); /* flush writes */
1501 BWN_RF_WRITE(mac, B2055_PLL_LFC2, e->radio_pll_lfc2);
1502 BWN_RF_WRITE(mac, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
1503 BWN_RF_WRITE(mac, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
1504 BWN_RF_WRITE(mac, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
1505 BWN_READ_4(mac, BWN_MACCTL); /* flush writes */
1507 BWN_RF_WRITE(mac, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
1508 BWN_RF_WRITE(mac, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
1509 BWN_RF_WRITE(mac, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
1510 BWN_RF_WRITE(mac, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
1511 BWN_READ_4(mac, BWN_MACCTL); /* flush writes */
1513 BWN_RF_WRITE(mac, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
1514 BWN_RF_WRITE(mac, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
1515 BWN_RF_WRITE(mac, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
1516 BWN_RF_WRITE(mac, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
1517 BWN_READ_4(mac, BWN_MACCTL); /* flush writes */
1519 BWN_RF_WRITE(mac, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
1520 BWN_RF_WRITE(mac, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
1524 static void bwn_radio_2055_setup(struct bwn_mac *mac,
1528 if (mac->mac_phy.rev >= 3) {
1529 BWN_ERRPRINTF(mac->mac_sc, "%s: phy rev %d out of range\n",
1531 mac->mac_phy.rev);
1534 DPRINTF(mac->mac_sc, BWN_DEBUG_RF, "%s: called\n", __func__);
1536 bwn_chantab_radio_upload(mac, e);
1538 BWN_RF_WRITE(mac, B2055_VCO_CAL10, 0x05);
1539 BWN_RF_WRITE(mac, B2055_VCO_CAL10, 0x45);
1540 BWN_READ_4(mac, BWN_MACCTL); /* flush writes */
1541 BWN_RF_WRITE(mac, B2055_VCO_CAL10, 0x65);
1545 static void bwn_radio_init2055_pre(struct bwn_mac *mac)
1547 BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_CMD,
1549 BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD,
1552 BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD,
1556 static void bwn_radio_init2055_post(struct bwn_mac *mac)
1558 struct bwn_softc *sc = mac->mac_sc;
1559 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
1571 BWN_RF_MASK(mac, B2055_MASTER1, 0xFFF3);
1573 BWN_RF_MASK(mac, B2055_C1_RX_BB_REG, 0x7F);
1574 BWN_RF_MASK(mac, B2055_C2_RX_BB_REG, 0x7F);
1576 BWN_RF_SETMASK(mac, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
1577 BWN_RF_WRITE(mac, B2055_CAL_MISC, 0x3C);
1578 BWN_RF_MASK(mac, B2055_CAL_MISC, 0xFFBE);
1579 BWN_RF_SET(mac, B2055_CAL_LPOCTL, 0x80);
1580 BWN_RF_SET(mac, B2055_CAL_MISC, 0x1);
1582 BWN_RF_SET(mac, B2055_CAL_MISC, 0x40);
1583 if (!bwn_radio_wait_value(mac, B2055_CAL_COUT2, 0x80, 0x80, 10, 2000))
1584 BWN_ERRPRINTF(mac->mac_sc, "radio post init timeout\n");
1585 BWN_RF_MASK(mac, B2055_CAL_LPOCTL, 0xFF7F);
1586 bwn_switch_channel(mac, bwn_get_chan(mac));
1587 BWN_RF_WRITE(mac, B2055_C1_RX_BB_LPF, 0x9);
1588 BWN_RF_WRITE(mac, B2055_C2_RX_BB_LPF, 0x9);
1589 BWN_RF_WRITE(mac, B2055_C1_RX_BB_MIDACHP, 0x83);
1590 BWN_RF_WRITE(mac, B2055_C2_RX_BB_MIDACHP, 0x83);
1591 BWN_RF_SETMASK(mac, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
1592 BWN_RF_SETMASK(mac, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
1594 BWN_RF_SET(mac, B2055_C1_RX_RFSPC1, 0x2);
1595 BWN_RF_SET(mac, B2055_C2_RX_RFSPC1, 0x2);
1597 BWN_RF_MASK(mac, B2055_C1_RX_RFSPC1, 0xFFFD);
1598 BWN_RF_MASK(mac, B2055_C2_RX_RFSPC1, 0xFFFD);
1607 static void bwn_radio_init2055(struct bwn_mac *mac)
1609 bwn_radio_init2055_pre(mac);
1610 if (mac->mac_status < BWN_MAC_STATUS_INITED) {
1612 b2055_upload_inittab(mac, 0, 0);
1614 bool ghz5 = bwn_current_band(mac) == BWN_BAND_5G;
1615 b2055_upload_inittab(mac, ghz5, 0);
1617 bwn_radio_init2055_post(mac);
1625 static int bwn_nphy_load_samples(struct bwn_mac *mac,
1627 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
1633 BWN_ERRPRINTF(mac->mac_sc, "allocation for samples loading failed\n");
1637 bwn_nphy_stay_in_carrier_search(mac, 1);
1643 bwn_ntab_write_bulk(mac, BWN_NTAB32(17, 0), len, data);
1647 bwn_nphy_stay_in_carrier_search(mac, 0);
1652 static uint16_t bwn_nphy_gen_load_samples(struct bwn_mac *mac, uint32_t freq, uint16_t max,
1659 bw = bwn_is_40mhz(mac) ? 40 : 20;
1663 if (BWN_PHY_READ(mac, BWN_NPHY_BBCFG) & BWN_NPHY_BBCFG_RSTRX)
1668 if (bwn_is_40mhz(mac))
1676 BWN_ERRPRINTF(mac->mac_sc, "allocation for samples generation failed\n");
1689 i = bwn_nphy_load_samples(mac, samples, len);
1695 static void bwn_nphy_run_samples(struct bwn_mac *mac, uint16_t samps, uint16_t loops,
1699 struct bwn_phy *phy = &mac->mac_phy;
1700 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
1705 bwn_nphy_stay_in_carrier_search(mac, true);
1710 lpf_bw3 = BWN_PHY_READ(mac, BWN_NPHY_REV7_RF_CTL_OVER3) & 0x80;
1711 lpf_bw4 = BWN_PHY_READ(mac, BWN_NPHY_REV7_RF_CTL_OVER4) & 0x80;
1716 uint16_t value = bwn_nphy_read_lpf_ctl(mac, 0);
1718 bwn_nphy_rf_ctl_override_rev19(mac, 0x80, value,
1721 bwn_nphy_rf_ctl_override_rev7(mac, 0x80, value,
1728 tmp = bwn_ntab_read(mac, BWN_NTAB16(15, 87));
1733 tmp = !bwn_is_40mhz(mac) ? 0x6464 : 0x4747;
1734 bwn_ntab_write(mac, BWN_NTAB16(15, 87), tmp);
1737 BWN_PHY_WRITE(mac, BWN_NPHY_SAMP_DEPCNT, (samps - 1));
1740 BWN_PHY_WRITE(mac, BWN_NPHY_SAMP_LOOPCNT, (loops - 1));
1742 BWN_PHY_WRITE(mac, BWN_NPHY_SAMP_LOOPCNT, loops);
1744 BWN_PHY_WRITE(mac, BWN_NPHY_SAMP_WAITCNT, wait);
1746 seq_mode = BWN_PHY_READ(mac, BWN_NPHY_RFSEQMODE);
1748 BWN_PHY_SET(mac, BWN_NPHY_RFSEQMODE, BWN_NPHY_RFSEQMODE_CAOVER);
1750 BWN_PHY_MASK(mac, BWN_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1751 BWN_PHY_SET(mac, BWN_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1754 BWN_PHY_WRITE(mac, BWN_NPHY_SAMP_CMD, tmp);
1757 if (!(BWN_PHY_READ(mac, BWN_NPHY_RFSEQST) & 1)) {
1764 BWN_ERRPRINTF(mac->mac_sc, "run samples timeout\n");
1766 BWN_PHY_WRITE(mac, BWN_NPHY_RFSEQMODE, seq_mode);
1768 bwn_nphy_stay_in_carrier_search(mac, false);
1776 static void bwn_nphy_scale_offset_rssi(struct bwn_mac *mac, uint16_t scale,
1791 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1793 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1795 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1797 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1801 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0I_RSSI_X, tmp);
1803 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1805 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1I_RSSI_X, tmp);
1807 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1811 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1813 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1815 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1817 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1821 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0I_TBD, tmp);
1823 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0Q_TBD, tmp);
1825 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1I_TBD, tmp);
1827 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1Q_TBD, tmp);
1831 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0I_PWRDET, tmp);
1833 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0Q_PWRDET, tmp);
1835 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1I_PWRDET, tmp);
1837 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1Q_PWRDET, tmp);
1841 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0I_TSSI, tmp);
1843 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1I_TSSI, tmp);
1847 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0Q_TSSI, tmp);
1849 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1Q_TSSI, tmp);
1854 static void bwn_nphy_rssi_select_rev19(struct bwn_mac *mac, uint8_t code,
1860 static void bwn_nphy_rev3_rssi_select(struct bwn_mac *mac, uint8_t code,
1867 BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_OVER1, 0xFDFF);
1868 BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_OVER, 0xFDFF);
1869 BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_C1, 0xFCFF);
1870 BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_C2, 0xFCFF);
1871 BWN_PHY_MASK(mac, BWN_NPHY_TXF_40CO_B1S0, 0xFFDF);
1872 BWN_PHY_MASK(mac, BWN_NPHY_TXF_40CO_B32S1, 0xFFDF);
1873 BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1874 BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1882 BWN_PHY_SETMASK(mac, reg, 0xFDFF, 0x0200);
1890 BWN_PHY_SETMASK(mac, reg, 0xFCFF, 0);
1895 BWN_PHY_SETMASK(mac, reg, 0xFFC3, 0);
1898 val = (bwn_current_band(mac) == BWN_BAND_5G) ? 4 : 8;
1903 BWN_PHY_SET(mac, reg, val);
1908 BWN_PHY_SET(mac, reg, 0x0020);
1921 BWN_PHY_SETMASK(mac, reg, 0xFCFF, val);
1922 BWN_PHY_SETMASK(mac, reg, 0xF3FF, val << 2);
1927 bwn_current_band(mac);
1929 if (mac->mac_phy.rev < 7) {
1930 if (bwn_nphy_ipa(mac))
1936 BWN_RF_WRITE(mac, reg, val);
1942 BWN_PHY_SET(mac, reg, 0x0200);
1949 static void bwn_nphy_rev2_rssi_select(struct bwn_mac *mac, uint8_t code,
1973 BWN_PHY_SETMASK(mac, BWN_NPHY_AFECTL_C1, 0x0FFF, val);
1974 BWN_PHY_SETMASK(mac, BWN_NPHY_AFECTL_C2, 0x0FFF, val);
1977 BWN_PHY_SETMASK(mac, BWN_NPHY_RFCTL_RSSIO1, 0xFFCF,
1979 BWN_PHY_SETMASK(mac, BWN_NPHY_RFCTL_RSSIO2, 0xFFCF,
1984 BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_OVER, ~0x3000);
1986 BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_CMD,
1989 BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_OVER,
1994 BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_CMD,
1997 BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_OVER, ~0x1);
2000 BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER, 0x3000);
2002 BWN_PHY_SETMASK(mac, BWN_NPHY_RFCTL_CMD,
2007 BWN_PHY_SET(mac, BWN_NPHY_RFCTL_OVER,
2012 BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD,
2015 BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_OVER, ~0x1);
2021 static void bwn_nphy_rssi_select(struct bwn_mac *mac, uint8_t code,
2024 if (mac->mac_phy.rev >= 19)
2025 bwn_nphy_rssi_select_rev19(mac, code, type);
2026 else if (mac->mac_phy.rev >= 3)
2027 bwn_nphy_rev3_rssi_select(mac, code, type);
2029 bwn_nphy_rev2_rssi_select(mac, code, type);
2033 static void bwn_nphy_set_rssi_2055_vcm(struct bwn_mac *mac,
2040 BWN_RF_SETMASK(mac, B2055_C1_B0NB_RSSIVCM,
2042 BWN_RF_SETMASK(mac, B2055_C1_RX_BB_RSSICTL5,
2045 BWN_RF_SETMASK(mac, B2055_C2_B0NB_RSSIVCM,
2047 BWN_RF_SETMASK(mac, B2055_C2_RX_BB_RSSICTL5,
2052 BWN_RF_SETMASK(mac, B2055_C1_RX_BB_RSSICTL5,
2055 BWN_RF_SETMASK(mac, B2055_C2_RX_BB_RSSICTL5,
2062 static int bwn_nphy_poll_rssi(struct bwn_mac *mac, enum n_rssi_type rssi_type,
2072 if (mac->mac_phy.rev >= 3) {
2073 save_regs_phy[0] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_C1);
2074 save_regs_phy[1] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_C2);
2075 save_regs_phy[2] = BWN_PHY_READ(mac,
2077 save_regs_phy[3] = BWN_PHY_READ(mac,
2079 save_regs_phy[4] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_OVER1);
2080 save_regs_phy[5] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_OVER);
2081 save_regs_phy[6] = BWN_PHY_READ(mac, BWN_NPHY_TXF_40CO_B1S0);
2082 save_regs_phy[7] = BWN_PHY_READ(mac, BWN_NPHY_TXF_40CO_B32S1);
2085 save_regs_phy[0] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_C1);
2086 save_regs_phy[1] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_C2);
2087 save_regs_phy[2] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_OVER);
2088 save_regs_phy[3] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_CMD);
2089 save_regs_phy[4] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_OVER);
2090 save_regs_phy[5] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_RSSIO1);
2091 save_regs_phy[6] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_RSSIO2);
2096 bwn_nphy_rssi_select(mac, 5, rssi_type);
2098 if (mac->mac_phy.rev < 2) {
2099 save_regs_phy[8] = BWN_PHY_READ(mac, BWN_NPHY_GPIO_SEL);
2100 BWN_PHY_WRITE(mac, BWN_NPHY_GPIO_SEL, 5);
2107 if (mac->mac_phy.rev < 2) {
2108 s[0] = BWN_PHY_READ(mac, BWN_NPHY_GPIO_LOOUT);
2109 s[1] = BWN_PHY_READ(mac, BWN_NPHY_GPIO_HIOUT);
2111 s[0] = BWN_PHY_READ(mac, BWN_NPHY_RSSI1);
2112 s[1] = BWN_PHY_READ(mac, BWN_NPHY_RSSI2);
2123 if (mac->mac_phy.rev < 2)
2124 BWN_PHY_WRITE(mac, BWN_NPHY_GPIO_SEL, save_regs_phy[8]);
2126 if (mac->mac_phy.rev >= 3) {
2127 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C1, save_regs_phy[0]);
2128 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C2, save_regs_phy[1]);
2129 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_LUT_TRSW_UP1,
2131 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_LUT_TRSW_UP2,
2133 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER1, save_regs_phy[4]);
2134 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, save_regs_phy[5]);
2135 BWN_PHY_WRITE(mac, BWN_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
2136 BWN_PHY_WRITE(mac, BWN_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
2138 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C1, save_regs_phy[0]);
2139 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C2, save_regs_phy[1]);
2140 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, save_regs_phy[2]);
2141 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_CMD, save_regs_phy[3]);
2142 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_OVER, save_regs_phy[4]);
2143 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
2144 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
2151 static void bwn_nphy_rev3_rssi_cal(struct bwn_mac *mac)
2153 //struct bwn_phy *phy = &mac->mac_phy;
2154 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
2202 if (mac->mac_phy.rev >= 7) {
2214 class = bwn_nphy_classifier(mac, 0, 0);
2215 bwn_nphy_classifier(mac, 7, 4);
2216 bwn_nphy_read_clip_detection(mac, clip_state);
2217 bwn_nphy_write_clip_detection(mac, clip_off);
2219 saved_regs_phy_rfctl[0] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_INTC1);
2220 saved_regs_phy_rfctl[1] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_INTC2);
2222 saved_regs_phy[i] = BWN_PHY_READ(mac, regs_to_store[i]);
2224 bwn_nphy_rf_ctl_intc_override(mac, N_INTC_OVERRIDE_OFF, 0, 7);
2225 bwn_nphy_rf_ctl_intc_override(mac, N_INTC_OVERRIDE_TRSW, 1, 7);
2227 if (mac->mac_phy.rev >= 7) {
2228 bwn_nphy_rf_ctl_override_one_to_many(mac,
2231 bwn_nphy_rf_ctl_override_one_to_many(mac,
2234 bwn_nphy_rf_ctl_override_rev7(mac, 0x80, 1, 0, false, 0);
2235 bwn_nphy_rf_ctl_override_rev7(mac, 0x40, 1, 0, false, 0);
2236 if (bwn_current_band(mac) == BWN_BAND_5G) {
2237 bwn_nphy_rf_ctl_override_rev7(mac, 0x20, 0, 0, false,
2239 bwn_nphy_rf_ctl_override_rev7(mac, 0x10, 1, 0, false,
2242 bwn_nphy_rf_ctl_override_rev7(mac, 0x10, 0, 0, false,
2244 bwn_nphy_rf_ctl_override_rev7(mac, 0x20, 1, 0, false,
2248 bwn_nphy_rf_ctl_override(mac, 0x1, 0, 0, false);
2249 bwn_nphy_rf_ctl_override(mac, 0x2, 1, 0, false);
2250 bwn_nphy_rf_ctl_override(mac, 0x80, 1, 0, false);
2251 bwn_nphy_rf_ctl_override(mac, 0x40, 1, 0, false);
2252 if (bwn_current_band(mac) == BWN_BAND_5G) {
2253 bwn_nphy_rf_ctl_override(mac, 0x20, 0, 0, false);
2254 bwn_nphy_rf_ctl_override(mac, 0x10, 1, 0, false);
2256 bwn_nphy_rf_ctl_override(mac, 0x10, 0, 0, false);
2257 bwn_nphy_rf_ctl_override(mac, 0x20, 1, 0, false);
2261 rx_core_state = bwn_nphy_get_rx_core_state(mac);
2266 bwn_nphy_scale_offset_rssi(mac, 0, 0, core + 1, N_RAIL_I,
2268 bwn_nphy_scale_offset_rssi(mac, 0, 0, core + 1, N_RAIL_Q,
2273 if (mac->mac_phy.rev >= 7)
2274 BWN_RF_SETMASK(mac,
2279 BWN_RF_SETMASK(mac, r | B2056_RX_RSSI_MISC,
2281 bwn_nphy_poll_rssi(mac, N_RSSI_NB, results[vcm], 8);
2307 if (mac->mac_phy.rev >= 7)
2308 BWN_RF_SETMASK(mac,
2313 BWN_RF_SETMASK(mac, r | B2056_RX_RSSI_MISC,
2326 bwn_nphy_scale_offset_rssi(mac, 0, offset[i],
2337 bwn_nphy_scale_offset_rssi(mac, 0, 0, core + 1,
2339 bwn_nphy_scale_offset_rssi(mac, 0, 0, core + 1,
2341 bwn_nphy_poll_rssi(mac, i, poll_results, 8);
2349 bwn_nphy_scale_offset_rssi(mac, 0,
2356 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC1, saved_regs_phy_rfctl[0]);
2357 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC2, saved_regs_phy_rfctl[1]);
2359 bwn_nphy_force_rf_sequence(mac, BWN_RFSEQ_RESET2RX);
2361 BWN_PHY_SET(mac, BWN_NPHY_TXF_40CO_B1S1, 0x1);
2362 BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD, BWN_NPHY_RFCTL_CMD_START);
2363 BWN_PHY_MASK(mac, BWN_NPHY_TXF_40CO_B1S1, ~0x1);
2365 BWN_PHY_SET(mac, BWN_NPHY_RFCTL_OVER, 0x1);
2366 BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD, BWN_NPHY_RFCTL_CMD_RXTX);
2367 BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_OVER, ~0x1);
2370 BWN_PHY_WRITE(mac, regs_to_store[i], saved_regs_phy[i]);
2373 if (bwn_current_band(mac) == BWN_BAND_2G) {
2380 if (mac->mac_phy.rev >= 7) {
2381 rssical_radio_regs[0] = BWN_RF_READ(mac,
2383 rssical_radio_regs[1] = BWN_RF_READ(mac,
2386 rssical_radio_regs[0] = BWN_RF_READ(mac, B2056_RX0 |
2388 rssical_radio_regs[1] = BWN_RF_READ(mac, B2056_RX1 |
2391 rssical_phy_regs[0] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_0I_RSSI_Z);
2392 rssical_phy_regs[1] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_0Q_RSSI_Z);
2393 rssical_phy_regs[2] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_1I_RSSI_Z);
2394 rssical_phy_regs[3] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_1Q_RSSI_Z);
2395 rssical_phy_regs[4] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_0I_RSSI_X);
2396 rssical_phy_regs[5] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_0Q_RSSI_X);
2397 rssical_phy_regs[6] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_1I_RSSI_X);
2398 rssical_phy_regs[7] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_1Q_RSSI_X);
2399 rssical_phy_regs[8] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_0I_RSSI_Y);
2400 rssical_phy_regs[9] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_0Q_RSSI_Y);
2401 rssical_phy_regs[10] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_1I_RSSI_Y);
2402 rssical_phy_regs[11] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_1Q_RSSI_Y);
2405 if (bwn_current_band(mac) == BWN_BAND_2G)
2406 nphy->rssical_chanspec_2G.center_freq = bwn_get_centre_freq(mac);
2408 nphy->rssical_chanspec_5G.center_freq = bwn_get_centre_freq(mac);
2411 bwn_nphy_classifier(mac, 7, class);
2412 bwn_nphy_write_clip_detection(mac, clip_state);
2416 static void bwn_nphy_rev2_rssi_cal(struct bwn_mac *mac, enum n_rssi_type type)
2443 BWN_ERRPRINTF(mac->mac_sc, "%s: RSSI type %d invalid\n",
2449 class = bwn_nphy_classifier(mac, 0, 0);
2450 bwn_nphy_classifier(mac, 7, 4);
2451 bwn_nphy_read_clip_detection(mac, clip_state);
2452 bwn_nphy_write_clip_detection(mac, clip_off);
2454 if (bwn_current_band(mac) == BWN_BAND_5G)
2459 regs_save_phy[0] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_INTC1);
2460 regs_save_radio[0] = BWN_RF_READ(mac, B2055_C1_PD_RXTX);
2461 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC1, override);
2462 BWN_RF_WRITE(mac, B2055_C1_PD_RXTX, val);
2464 regs_save_phy[1] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_INTC2);
2465 regs_save_radio[1] = BWN_RF_READ(mac, B2055_C2_PD_RXTX);
2466 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC2, override);
2467 BWN_RF_WRITE(mac, B2055_C2_PD_RXTX, val);
2469 state[0] = BWN_RF_READ(mac, B2055_C1_PD_RSSIMISC) & 0x07;
2470 state[1] = BWN_RF_READ(mac, B2055_C2_PD_RSSIMISC) & 0x07;
2471 BWN_RF_MASK(mac, B2055_C1_PD_RSSIMISC, 0xF8);
2472 BWN_RF_MASK(mac, B2055_C2_PD_RSSIMISC, 0xF8);
2473 state[2] = BWN_RF_READ(mac, B2055_C1_SP_RSSI) & 0x07;
2474 state[3] = BWN_RF_READ(mac, B2055_C2_SP_RSSI) & 0x07;
2476 bwn_nphy_rssi_select(mac, 5, type);
2477 bwn_nphy_scale_offset_rssi(mac, 0, 0, 5, N_RAIL_I, type);
2478 bwn_nphy_scale_offset_rssi(mac, 0, 0, 5, N_RAIL_Q, type);
2485 bwn_nphy_set_rssi_2055_vcm(mac, type, tmp);
2486 bwn_nphy_poll_rssi(mac, type, results[vcm], 8);
2517 bwn_nphy_set_rssi_2055_vcm(mac, type, vcm_final);
2533 bwn_nphy_scale_offset_rssi(mac, 0, offset[i], core, rail,
2537 BWN_RF_SETMASK(mac, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
2538 BWN_RF_SETMASK(mac, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
2542 bwn_nphy_rssi_select(mac, 1, N_RSSI_NB);
2545 bwn_nphy_rssi_select(mac, 1, N_RSSI_W1);
2548 bwn_nphy_rssi_select(mac, 1, N_RSSI_W2);
2551 bwn_nphy_rssi_select(mac, 1, N_RSSI_W2);
2557 bwn_nphy_rssi_select(mac, 2, N_RSSI_NB);
2560 bwn_nphy_rssi_select(mac, 2, N_RSSI_W1);
2563 bwn_nphy_rssi_select(mac, 2, N_RSSI_W2);
2567 bwn_nphy_rssi_select(mac, 0, type);
2569 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC1, regs_save_phy[0]);
2570 BWN_RF_WRITE(mac, B2055_C1_PD_RXTX, regs_save_radio[0]);
2571 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC2, regs_save_phy[1]);
2572 BWN_RF_WRITE(mac, B2055_C2_PD_RXTX, regs_save_radio[1]);
2574 bwn_nphy_classifier(mac, 7, class);
2575 bwn_nphy_write_clip_detection(mac, clip_state);
2578 bwn_nphy_reset_cca(mac);
2585 static void bwn_nphy_rssi_cal(struct bwn_mac *mac)
2587 if (mac->mac_phy.rev >= 19) {
2589 } else if (mac->mac_phy.rev >= 3) {
2590 bwn_nphy_rev3_rssi_cal(mac);
2592 bwn_nphy_rev2_rssi_cal(mac, N_RSSI_NB);
2593 bwn_nphy_rev2_rssi_cal(mac, N_RSSI_W1);
2594 bwn_nphy_rev2_rssi_cal(mac, N_RSSI_W2);
2602 static void bwn_nphy_gain_ctl_workarounds_rev19(struct bwn_mac *mac)
2607 static void bwn_nphy_gain_ctl_workarounds_rev7(struct bwn_mac *mac)
2609 struct bwn_phy *phy = &mac->mac_phy;
2616 static void bwn_nphy_gain_ctl_workarounds_rev3(struct bwn_mac *mac)
2618 struct bwn_softc *sc = mac->mac_sc;
2627 ghz5 = BWN_PHY_READ(mac, BWN_NPHY_BANDCTL)
2631 e = bwn_nphy_get_gain_ctl_workaround_ent(mac, ghz5, ext_lna);
2632 if (ghz5 && mac->mac_phy.rev >= 5)
2637 BWN_PHY_SET(mac, BWN_NPHY_RXCTL, 0x0040);
2640 BWN_PHY_SET(mac, BWN_NPHY_C1_CGAINI, BWN_NPHY_C1_CGAINI_CL2DETECT);
2641 BWN_PHY_SET(mac, BWN_NPHY_C2_CGAINI, BWN_NPHY_C2_CGAINI_CL2DETECT);
2643 BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
2645 BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
2647 BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
2648 BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
2649 BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
2650 BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
2651 BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_RSSI_GAIN,
2653 BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_RSSI_GAIN,
2655 BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
2657 BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
2659 BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
2660 BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
2662 bwn_ntab_write_bulk(mac, BWN_NTAB8(0, 8), 4, e->lna1_gain);
2663 bwn_ntab_write_bulk(mac, BWN_NTAB8(1, 8), 4, e->lna1_gain);
2664 bwn_ntab_write_bulk(mac, BWN_NTAB8(0, 16), 4, e->lna2_gain);
2665 bwn_ntab_write_bulk(mac, BWN_NTAB8(1, 16), 4, e->lna2_gain);
2666 bwn_ntab_write_bulk(mac, BWN_NTAB8(0, 32), 10, e->gain_db);
2667 bwn_ntab_write_bulk(mac, BWN_NTAB8(1, 32), 10, e->gain_db);
2668 bwn_ntab_write_bulk(mac, BWN_NTAB8(2, 32), 10, e->gain_bits);
2669 bwn_ntab_write_bulk(mac, BWN_NTAB8(3, 32), 10, e->gain_bits);
2670 bwn_ntab_write_bulk(mac, BWN_NTAB8(0, 0x40), 6, lpf_gain);
2671 bwn_ntab_write_bulk(mac, BWN_NTAB8(1, 0x40), 6, lpf_gain);
2672 bwn_ntab_write_bulk(mac, BWN_NTAB8(2, 0x40), 6, lpf_bits);
2673 bwn_ntab_write_bulk(mac, BWN_NTAB8(3, 0x40), 6, lpf_bits);
2675 BWN_PHY_WRITE(mac, BWN_NPHY_REV3_C1_INITGAIN_A, e->init_gain);
2676 BWN_PHY_WRITE(mac, BWN_NPHY_REV3_C2_INITGAIN_A, e->init_gain);
2678 bwn_ntab_write_bulk(mac, BWN_NTAB16(7, 0x106), 2,
2681 BWN_PHY_WRITE(mac, BWN_NPHY_REV3_C1_CLIP_HIGAIN_A, e->cliphi_gain);
2682 BWN_PHY_WRITE(mac, BWN_NPHY_REV3_C2_CLIP_HIGAIN_A, e->cliphi_gain);
2683 BWN_PHY_WRITE(mac, BWN_NPHY_REV3_C1_CLIP_MEDGAIN_A, e->clipmd_gain);
2684 BWN_PHY_WRITE(mac, BWN_NPHY_REV3_C2_CLIP_MEDGAIN_A, e->clipmd_gain);
2685 BWN_PHY_WRITE(mac, BWN_NPHY_REV3_C1_CLIP_LOGAIN_A, e->cliplo_gain);
2686 BWN_PHY_WRITE(mac, BWN_NPHY_REV3_C2_CLIP_LOGAIN_A, e->cliplo_gain);
2688 BWN_PHY_SETMASK(mac, BWN_NPHY_CRSMINPOWER0, 0xFF00, e->crsmin);
2689 BWN_PHY_SETMASK(mac, BWN_NPHY_CRSMINPOWERL0, 0xFF00, e->crsminl);
2690 BWN_PHY_SETMASK(mac, BWN_NPHY_CRSMINPOWERU0, 0xFF00, e->crsminu);
2691 BWN_PHY_WRITE(mac, BWN_NPHY_C1_NBCLIPTHRES, e->nbclip);
2692 BWN_PHY_WRITE(mac, BWN_NPHY_C2_NBCLIPTHRES, e->nbclip);
2693 BWN_PHY_SETMASK(mac, BWN_NPHY_C1_CLIPWBTHRES,
2695 BWN_PHY_SETMASK(mac, BWN_NPHY_C2_CLIPWBTHRES,
2697 BWN_PHY_WRITE(mac, BWN_NPHY_CCK_SHIFTB_REF, 0x809C);
2700 static void bwn_nphy_gain_ctl_workarounds_rev1_2(struct bwn_mac *mac)
2702 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
2711 BWN_PHY_SET(mac, BWN_NPHY_C1_CGAINI, BWN_NPHY_C1_CGAINI_CL2DETECT);
2712 BWN_PHY_SET(mac, BWN_NPHY_C2_CGAINI, BWN_NPHY_C2_CGAINI_CL2DETECT);
2715 BWN_PHY_WRITE(mac, BWN_NPHY_C1_NBCLIPTHRES, 0x84);
2716 BWN_PHY_WRITE(mac, BWN_NPHY_C2_NBCLIPTHRES, 0x84);
2718 if (!bwn_is_40mhz(mac)) {
2720 BWN_PHY_WRITE(mac, BWN_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
2721 BWN_PHY_WRITE(mac, BWN_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
2722 BWN_PHY_WRITE(mac, BWN_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
2723 BWN_PHY_WRITE(mac, BWN_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
2727 BWN_PHY_SETMASK(mac, BWN_NPHY_C1_CLIPWBTHRES,
2729 BWN_PHY_SETMASK(mac, BWN_NPHY_C2_CLIPWBTHRES,
2732 if (!bwn_is_40mhz(mac)) {
2733 BWN_PHY_SETMASK(mac, BWN_NPHY_C1_CGAINI,
2735 BWN_PHY_SETMASK(mac, BWN_NPHY_C2_CGAINI,
2737 BWN_PHY_SETMASK(mac, BWN_NPHY_C1_CCK_CGAINI,
2739 BWN_PHY_SETMASK(mac, BWN_NPHY_C2_CCK_CGAINI,
2743 BWN_PHY_WRITE(mac, BWN_NPHY_CCK_SHIFTB_REF, 0x809C);
2746 if (bwn_current_band(mac) == BWN_BAND_2G &&
2747 bwn_is_40mhz(mac))
2752 code = bwn_is_40mhz(mac) ? 6 : 7;
2756 BWN_PHY_SETMASK(mac, BWN_NPHY_C1_INITGAIN, ~BWN_NPHY_C1_INITGAIN_HPVGA2,
2758 BWN_PHY_SETMASK(mac, BWN_NPHY_C2_INITGAIN, ~BWN_NPHY_C2_INITGAIN_HPVGA2,
2761 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, 0x1D06);
2764 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, (code << 8 | 0x7C));
2766 bwn_nphy_adjust_lna_gain_table(mac);
2769 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, 0x0808);
2770 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, 0x0);
2771 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, 0x1);
2772 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, 0x1);
2773 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, 0x1);
2775 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, 0x0C08);
2776 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, 0x0);
2777 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, 0x1);
2778 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, 0x1);
2779 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, 0x1);
2781 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, 0x1D06);
2784 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO,
2788 if (mac->mac_phy.rev == 2) {
2790 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR,
2794 BWN_PHY_WRITE(mac,
2800 bwn_nphy_set_rf_sequence(mac, 5, rfseq_events, rfseq_delays, 3);
2801 BWN_PHY_SETMASK(mac, BWN_NPHY_OVER_DGAIN1,
2805 if (bwn_current_band(mac) == BWN_BAND_2G)
2806 BWN_PHY_SETMASK(mac, BWN_PHY_N(0xC5D), 0xFF80, 4);
2810 static void bwn_nphy_gain_ctl_workarounds(struct bwn_mac *mac)
2812 if (mac->mac_phy.rev >= 19)
2813 bwn_nphy_gain_ctl_workarounds_rev19(mac);
2814 else if (mac->mac_phy.rev >= 7)
2815 bwn_nphy_gain_ctl_workarounds_rev7(mac);
2816 else if (mac->mac_phy.rev >= 3)
2817 bwn_nphy_gain_ctl_workarounds_rev3(mac);
2819 bwn_nphy_gain_ctl_workarounds_rev1_2(mac);
2822 static int bwn_nphy_workarounds_rev7plus(struct bwn_mac *mac)
2824 struct bwn_softc *sc = mac->mac_sc;
2825 struct bwn_phy *phy = &mac->mac_phy;
2853 BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_A0, 0x0125);
2854 BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_A1, 0x01b3);
2855 BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_A2, 0x0105);
2856 BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_B0, 0x016e);
2857 BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_B1, 0x00cd);
2858 BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_B2, 0x0020);
2861 BWN_PHY_SET(mac, BWN_NPHY_FINERX2_CGC, 0x10);
2862 BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN0, 0xFF80, 0x0020);
2863 BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN0, 0x80FF, 0x2700);
2864 BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN1, 0xFF80, 0x002E);
2865 BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN1, 0x80FF, 0x3300);
2866 BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN2, 0xFF80, 0x0037);
2867 BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN2, 0x80FF, 0x3A00);
2868 BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN3, 0xFF80, 0x003C);
2869 BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN3, 0x80FF, 0x3E00);
2870 BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN4, 0xFF80, 0x003E);
2871 BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN4, 0x80FF, 0x3F00);
2872 BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN5, 0xFF80, 0x0040);
2873 BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN5, 0x80FF, 0x4000);
2874 BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN6, 0xFF80, 0x0040);
2875 BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN6, 0x80FF, 0x4000);
2876 BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN7, 0xFF80, 0x0040);
2877 BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN7, 0x80FF, 0x4000);
2881 BWN_PHY_WRITE(mac, BWN_NPHY_FORCEFRONT0, 0x7ff);
2882 BWN_PHY_WRITE(mac, BWN_NPHY_FORCEFRONT1, 0x7ff);
2884 BWN_PHY_WRITE(mac, BWN_NPHY_FORCEFRONT0, 0x1B0);
2885 BWN_PHY_WRITE(mac, BWN_NPHY_FORCEFRONT1, 0x1B0);
2889 BWN_PHY_SETMASK(mac, BWN_NPHY_TXTAILCNT, ~0xFF, 0xa0);
2891 BWN_PHY_SETMASK(mac, BWN_NPHY_TXTAILCNT, ~0xFF, 0x72);
2893 bwn_ntab_write(mac, BWN_NTAB16(8, 0x00), 2);
2894 bwn_ntab_write(mac, BWN_NTAB16(8, 0x10), 2);
2895 tmp32 = bwn_ntab_read(mac, BWN_NTAB32(30, 0));
2897 bwn_ntab_write(mac, BWN_NTAB32(30, 0), tmp32);
2898 bwn_ntab_write_bulk(mac, BWN_NTAB16(7, 0x15d), 3, ntab7_15e_16e);
2899 bwn_ntab_write_bulk(mac, BWN_NTAB16(7, 0x16d), 3, ntab7_15e_16e);
2901 bwn_nphy_set_rf_sequence(mac, 1, tx2rx_events, tx2rx_delays,
2903 if (bwn_nphy_ipa(mac))
2904 bwn_nphy_set_rf_sequence(mac, 0, rx2tx_events_ipa,
2907 BWN_PHY_SETMASK(mac, BWN_NPHY_EPS_OVERRIDEI_0, 0x3FFF, 0x4000);
2908 BWN_PHY_SETMASK(mac, BWN_NPHY_EPS_OVERRIDEI_1, 0x3FFF, 0x4000);
2911 lpf_ofdm_20mhz[core] = bwn_nphy_read_lpf_ctl(mac, 0x154 + core * 0x10);
2912 lpf_ofdm_40mhz[core] = bwn_nphy_read_lpf_ctl(mac, 0x159 + core * 0x10);
2913 lpf_11b[core] = bwn_nphy_read_lpf_ctl(mac, 0x152 + core * 0x10);
2916 bcap_val = BWN_RF_READ(mac, R2057_RCCAL_BCAP_VAL);
2917 scap_val = BWN_RF_READ(mac, R2057_RCCAL_SCAP_VAL);
2919 if (bwn_nphy_ipa(mac)) {
2920 bool ghz2 = bwn_current_band(mac) == BWN_BAND_2G;
2925 if (phy->rev == 8 && bwn_is_40mhz(mac)) {
2948 if (bwn_current_band(mac) == BWN_BAND_2G) {
3059 bwn_ntab_write(mac, BWN_NTAB16(7, 0x152 + core * 16),
3061 bwn_ntab_write(mac, BWN_NTAB16(7, 0x153 + core * 16),
3063 bwn_ntab_write(mac, BWN_NTAB16(7, 0x154 + core * 16),
3065 bwn_ntab_write(mac, BWN_NTAB16(7, 0x155 + core * 16),
3067 bwn_ntab_write(mac, BWN_NTAB16(7, 0x156 + core * 16),
3069 bwn_ntab_write(mac, BWN_NTAB16(7, 0x157 + core * 16),
3071 bwn_ntab_write(mac, BWN_NTAB16(7, 0x158 + core * 16),
3073 bwn_ntab_write(mac, BWN_NTAB16(7, 0x159 + core * 16),
3078 BWN_PHY_WRITE(mac, 0x32F, 0x3);
3081 bwn_nphy_rf_ctl_override_rev7(mac, 4, 1, 3, false, 0);
3086 BWN_RF_WRITE(mac, 0x5, 0x05);
3087 BWN_RF_WRITE(mac, 0x6, 0x30);
3088 BWN_RF_WRITE(mac, 0x7, 0x00);
3089 BWN_RF_SET(mac, 0x4f, 0x1);
3090 BWN_RF_SET(mac, 0xd4, 0x1);
3099 if (bwn_current_band(mac) == BWN_BAND_2G) {
3102 BWN_RF_WRITE(mac, 0x5F, bias);
3103 BWN_RF_WRITE(mac, 0x64, conv);
3104 BWN_RF_WRITE(mac, 0x66, filt);
3106 BWN_RF_WRITE(mac, 0xE8, bias);
3107 BWN_RF_WRITE(mac, 0xE9, conv);
3108 BWN_RF_WRITE(mac, 0xEB, filt);
3114 if (bwn_nphy_ipa(mac)) {
3115 if (bwn_current_band(mac) == BWN_BAND_2G) {
3120 BWN_RF_WRITE(mac, 0x51,
3123 BWN_RF_WRITE(mac, 0xd6,
3131 BWN_RF_WRITE(mac, 0x64,
3133 BWN_RF_WRITE(mac, 0x5F,
3135 BWN_RF_WRITE(mac, 0x66,
3137 BWN_RF_WRITE(mac, 0x59,
3139 BWN_RF_WRITE(mac, 0x80,
3142 BWN_RF_WRITE(mac, 0x69,
3144 BWN_RF_WRITE(mac, 0xE8,
3146 BWN_RF_WRITE(mac, 0xEB,
3148 BWN_RF_WRITE(mac, 0xDE,
3150 BWN_RF_WRITE(mac, 0x105,
3157 if (!bwn_is_40mhz(mac)) {
3158 BWN_RF_WRITE(mac, 0x5F, 0x14);
3159 BWN_RF_WRITE(mac, 0xE8, 0x12);
3161 BWN_RF_WRITE(mac, 0x5F, 0x16);
3162 BWN_RF_WRITE(mac, 0xE8, 0x16);
3169 BWN_RF_WRITE(mac, o + R2057_IPA2G_CASCONV_CORE0, 0x13);
3170 BWN_RF_WRITE(mac, o + R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, 0x21);
3171 BWN_RF_WRITE(mac, o + R2057_IPA2G_BIAS_FILTER_CORE0, 0xff);
3172 BWN_RF_WRITE(mac, o + R2057_PAD2G_IDACS_CORE0, 0x88);
3173 BWN_RF_WRITE(mac, o + R2057_PAD2G_TUNE_PUS_CORE0, 0x23);
3174 BWN_RF_WRITE(mac, o + R2057_IPA2G_IMAIN_CORE0, 0x16);
3175 BWN_RF_WRITE(mac, o + R2057_PAD_BIAS_FILTER_BWS_CORE0, 0x3e);
3176 BWN_RF_WRITE(mac, o + R2057_BACKUP1_CORE0, 0x10);
3181 uint16_t freq = bwn_get_centre_freq(mac);
3184 BWN_RF_WRITE(mac, 0x7D, 0xFF);
3185 BWN_RF_WRITE(mac, 0xFE, 0xFF);
3192 BWN_RF_WRITE(mac, 0x5c, 0x61);
3193 BWN_RF_WRITE(mac, 0x51, 0x70);
3195 BWN_RF_WRITE(mac, 0xe1, 0x61);
3196 BWN_RF_WRITE(mac, 0xd6, 0x70);
3203 bwn_ntab_write(mac, BWN_NTAB16(8, 0x05), 0x20);
3204 bwn_ntab_write(mac, BWN_NTAB16(8, 0x15), 0x20);
3207 BWN_RF_WRITE(mac, 0x1a1, 0x00);
3208 BWN_RF_WRITE(mac, 0x1a2, 0x3f);
3209 BWN_RF_WRITE(mac, 0x1a6, 0x3f);
3211 BWN_RF_WRITE(mac, 0x1a7, 0x00);
3212 BWN_RF_WRITE(mac, 0x1ab, 0x3f);
3213 BWN_RF_WRITE(mac, 0x1ac, 0x3f);
3217 BWN_PHY_SET(mac, BWN_NPHY_AFECTL_C1, 0x4);
3218 BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER1, 0x4);
3219 BWN_PHY_SET(mac, BWN_NPHY_AFECTL_C2, 0x4);
3220 BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER, 0x4);
3222 BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_C1, ~0x1);
3223 BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER1, 0x1);
3224 BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_C2, ~0x1);
3225 BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER, 0x1);
3226 bwn_ntab_write(mac, BWN_NTAB16(8, 0x05), 0);
3227 bwn_ntab_write(mac, BWN_NTAB16(8, 0x15), 0);
3229 BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_C1, ~0x4);
3230 BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_OVER1, ~0x4);
3231 BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_C2, ~0x4);
3232 BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_OVER, ~0x4);
3235 BWN_PHY_WRITE(mac, BWN_NPHY_ENDROP_TLEN, 0x2);
3237 bwn_ntab_write(mac, BWN_NTAB32(16, 0x100), 20);
3238 bwn_ntab_write_bulk(mac, BWN_NTAB8(7, 0x138), 2, ntab7_138_146);
3239 bwn_ntab_write(mac, BWN_NTAB16(7, 0x141), 0x77);
3240 bwn_ntab_write_bulk(mac, BWN_NTAB8(7, 0x133), 3, ntab7_133);
3241 bwn_ntab_write_bulk(mac, BWN_NTAB8(7, 0x146), 2, ntab7_138_146);
3242 bwn_ntab_write(mac, BWN_NTAB16(7, 0x123), 0x77);
3243 bwn_ntab_write(mac, BWN_NTAB16(7, 0x12A), 0x77);
3245 bwn_ntab_read_bulk(mac, BWN_NTAB32(16, 0x02), 1, noise_tbl);
3246 noise_tbl[1] = bwn_is_40mhz(mac) ? 0x14D : 0x18D;
3247 bwn_ntab_write_bulk(mac, BWN_NTAB32(16, 0x02), 2, noise_tbl);
3249 bwn_ntab_read_bulk(mac, BWN_NTAB32(16, 0x7E), 1, noise_tbl);
3250 noise_tbl[1] = bwn_is_40mhz(mac) ? 0x14D : 0x18D;
3251 bwn_ntab_write_bulk(mac, BWN_NTAB32(16, 0x7E), 2, noise_tbl);
3253 bwn_nphy_gain_ctl_workarounds(mac);
3256 bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x08), 4,
3258 bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x18), 4,
3260 bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x0C), 4,
3262 bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x1C), 4,
3269 static int bwn_nphy_workarounds_rev3plus(struct bwn_mac *mac)
3271 struct bwn_softc *sc = mac->mac_sc;
3272 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
3306 BWN_PHY_WRITE(mac, BWN_NPHY_FORCEFRONT0, 0x1f8);
3307 BWN_PHY_WRITE(mac, BWN_NPHY_FORCEFRONT1, 0x1f8);
3309 tmp32 = bwn_ntab_read(mac, BWN_NTAB32(30, 0));
3311 bwn_ntab_write(mac, BWN_NTAB32(30, 0), tmp32);
3313 BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_A0, 0x0125);
3314 BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_A1, 0x01B3);
3315 BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_A2, 0x0105);
3316 BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_B0, 0x016E);
3317 BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_B1, 0x00CD);
3318 BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_B2, 0x0020);
3320 BWN_PHY_WRITE(mac, BWN_NPHY_REV3_C1_CLIP_LOGAIN_B, 0x000C);
3321 BWN_PHY_WRITE(mac, BWN_NPHY_REV3_C2_CLIP_LOGAIN_B, 0x000C);
3324 bwn_nphy_set_rf_sequence(mac, 1, tx2rx_events, tx2rx_delays,
3328 if (bwn_nphy_ipa(mac))
3329 bwn_nphy_set_rf_sequence(mac, 0, rx2tx_events_ipa,
3333 if (bwn_nphy_ipa(mac)) {
3338 bwn_nphy_set_rf_sequence(mac, 0, rx2tx_events, rx2tx_delays,
3342 tmp16 = (bwn_current_band(mac) == BWN_BAND_2G) ?
3344 BWN_PHY_WRITE(mac, BWN_NPHY_ENDROP_TLEN, tmp16);
3346 BWN_PHY_SETMASK(mac, BWN_NPHY_SGILTRNOFFSET, 0xF0FF, 0x0700);
3348 if (!bwn_is_40mhz(mac)) {
3349 bwn_ntab_write(mac, BWN_NTAB32(16, 3), 0x18D);
3350 bwn_ntab_write(mac, BWN_NTAB32(16, 127), 0x18D);
3352 bwn_ntab_write(mac, BWN_NTAB32(16, 3), 0x14D);
3353 bwn_ntab_write(mac, BWN_NTAB32(16, 127), 0x14D);
3356 bwn_nphy_gain_ctl_workarounds(mac);
3358 bwn_ntab_write(mac, BWN_NTAB16(8, 0), 2);
3359 bwn_ntab_write(mac, BWN_NTAB16(8, 16), 2);
3361 if (bwn_current_band(mac) == BWN_BAND_2G)
3369 BWN_ERRPRINTF(mac->mac_sc, "Error reading PDet range %s from "
3379 if (!(mac->mac_phy.rev >= 4 &&
3380 bwn_current_band(mac) == BWN_BAND_2G))
3385 bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x08), 4, vmid);
3386 bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x18), 4, vmid);
3387 bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x0c), 4, gain);
3388 bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x1c), 4, gain);
3391 if (mac->mac_phy.rev >= 6) {
3392 if (bwn_current_band(mac) == BWN_BAND_2G)
3397 } else if (mac->mac_phy.rev == 5) {
3401 bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x08), 4, vmid);
3402 bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x18), 4, vmid);
3403 bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x0c), 4, gain);
3404 bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x1c), 4, gain);
3408 if (bwn_current_band(mac) != BWN_BAND_2G) {
3429 bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x08), 4, vmid);
3430 bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x0c), 4, gain);
3432 bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x18), 4, vmid);
3433 bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x1c), 4, gain);
3437 BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
3438 BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
3439 BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
3440 BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
3441 BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
3442 BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
3443 BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
3444 BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
3445 BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
3446 BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
3447 BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
3448 BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
3453 bwn_current_band(mac) == BWN_BAND_5G) ||
3455 bwn_current_band(mac) == BWN_BAND_2G))
3459 bwn_ntab_write(mac, BWN_NTAB32(30, 1), tmp32);
3460 bwn_ntab_write(mac, BWN_NTAB32(30, 2), tmp32);
3461 bwn_ntab_write(mac, BWN_NTAB32(30, 3), tmp32);
3463 if (mac->mac_phy.rev == 4 &&
3464 bwn_current_band(mac) == BWN_BAND_5G) {
3465 BWN_RF_WRITE(mac, B2056_TX0 | B2056_TX_GMBB_IDAC,
3467 BWN_RF_WRITE(mac, B2056_TX1 | B2056_TX_GMBB_IDAC,
3472 BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS40ASSERTTHRESH0, 0x03eb);
3473 BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS40ASSERTTHRESH1, 0x03eb);
3474 BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS40DEASSERTTHRESH0, 0x0341);
3475 BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS40DEASSERTTHRESH1, 0x0341);
3476 BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS20LASSERTTHRESH0, 0x042b);
3477 BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS20LASSERTTHRESH1, 0x042b);
3478 BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS20LDEASSERTTHRESH0, 0x0381);
3479 BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS20LDEASSERTTHRESH1, 0x0381);
3480 BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS20UASSERTTHRESH0, 0x042b);
3481 BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS20UASSERTTHRESH1, 0x042b);
3482 BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS20UDEASSERTTHRESH0, 0x0381);
3483 BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS20UDEASSERTTHRESH1, 0x0381);
3485 if (mac->mac_phy.rev >= 6 && sc->sc_board_info.board_flags2 & BHND_BFL2_SINGLEANT_CCK)
3491 static int bwn_nphy_workarounds_rev1_2(struct bwn_mac *mac)
3493 struct bwn_softc *sc = mac->mac_sc;
3494 struct bwn_phy *phy = &mac->mac_phy;
3509 if (bwn_current_band(mac) == BWN_BAND_5G &&
3511 BWN_RF_MASK(mac, B2055_C1_TX_RF_SPARE, ~0x8);
3512 BWN_RF_MASK(mac, B2055_C2_TX_RF_SPARE, ~0x8);
3514 BWN_RF_SET(mac, B2055_C1_TX_RF_SPARE, 0x8);
3515 BWN_RF_SET(mac, B2055_C2_TX_RF_SPARE, 0x8);
3518 bwn_ntab_write(mac, BWN_NTAB16(8, 0x00), 0x000A);
3519 bwn_ntab_write(mac, BWN_NTAB16(8, 0x10), 0x000A);
3520 if (mac->mac_phy.rev < 3) {
3521 bwn_ntab_write(mac, BWN_NTAB16(8, 0x02), 0xCDAA);
3522 bwn_ntab_write(mac, BWN_NTAB16(8, 0x12), 0xCDAA);
3525 if (mac->mac_phy.rev < 2) {
3526 bwn_ntab_write(mac, BWN_NTAB16(8, 0x08), 0x0000);
3527 bwn_ntab_write(mac, BWN_NTAB16(8, 0x18), 0x0000);
3528 bwn_ntab_write(mac, BWN_NTAB16(8, 0x07), 0x7AAB);
3529 bwn_ntab_write(mac, BWN_NTAB16(8, 0x17), 0x7AAB);
3530 bwn_ntab_write(mac, BWN_NTAB16(8, 0x06), 0x0800);
3531 bwn_ntab_write(mac, BWN_NTAB16(8, 0x16), 0x0800);
3534 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
3535 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
3536 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
3537 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
3539 bwn_nphy_set_rf_sequence(mac, 0, events1, delays1, 7);
3540 bwn_nphy_set_rf_sequence(mac, 1, events2, delays2, 7);
3542 bwn_nphy_gain_ctl_workarounds(mac);
3544 if (mac->mac_phy.rev < 2) {
3545 if (BWN_PHY_READ(mac, BWN_NPHY_RXCTL) & 0x2)
3546 bwn_hf_write(mac, bwn_hf_read(mac) |
3548 } else if (mac->mac_phy.rev == 2) {
3549 BWN_PHY_WRITE(mac, BWN_NPHY_CRSCHECK2, 0);
3550 BWN_PHY_WRITE(mac, BWN_NPHY_CRSCHECK3, 0);
3553 if (mac->mac_phy.rev < 2)
3554 BWN_PHY_MASK(mac, BWN_NPHY_SCRAM_SIGCTL,
3558 BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_A0, 0x125);
3559 BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_A1, 0x1B3);
3560 BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_A2, 0x105);
3561 BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_B0, 0x16E);
3562 BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_B1, 0xCD);
3563 BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_B2, 0x20);
3565 if (mac->mac_phy.rev < 3) {
3566 BWN_PHY_MASK(mac, BWN_NPHY_PIL_DW1,
3568 BWN_PHY_WRITE(mac, BWN_NPHY_TXF_20CO_S2B1, 0xB5);
3569 BWN_PHY_WRITE(mac, BWN_NPHY_TXF_20CO_S2B2, 0xA4);
3570 BWN_PHY_WRITE(mac, BWN_NPHY_TXF_20CO_S2B3, 0x00);
3573 if (mac->mac_phy.rev == 2)
3574 BWN_PHY_SET(mac, BWN_NPHY_FINERX2_CGC,
3581 static int bwn_nphy_workarounds(struct bwn_mac *mac)
3583 struct bwn_phy *phy = &mac->mac_phy;
3587 if (bwn_current_band(mac) == BWN_BAND_5G)
3588 bwn_nphy_classifier(mac, 1, 0);
3590 bwn_nphy_classifier(mac, 1, 1);
3593 bwn_nphy_stay_in_carrier_search(mac, 1);
3595 BWN_PHY_SET(mac, BWN_NPHY_IQFLIP,
3599 if (mac->mac_phy.rev >= 7)
3600 error = bwn_nphy_workarounds_rev7plus(mac);
3601 else if (mac->mac_phy.rev >= 3)
3602 error = bwn_nphy_workarounds_rev3plus(mac);
3604 error = bwn_nphy_workarounds_rev1_2(mac);
3610 bwn_nphy_stay_in_carrier_search(mac, 0);
3623 static int bwn_nphy_tx_tone(struct bwn_mac *mac, uint32_t freq, uint16_t max_val,
3626 uint16_t samp = bwn_nphy_gen_load_samples(mac, freq, max_val, dac_test);
3629 bwn_nphy_run_samples(mac, samp, 0xFFFF, 0, iqmode, dac_test,
3635 static void bwn_nphy_update_txrx_chain(struct bwn_mac *mac)
3637 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
3650 BWN_PHY_SETMASK(mac, BWN_NPHY_RFSEQCA,
3655 BWN_PHY_SET(mac, BWN_NPHY_RFSEQMODE,
3658 BWN_PHY_MASK(mac, BWN_NPHY_RFSEQMODE,
3663 static void bwn_nphy_stop_playback(struct bwn_mac *mac)
3665 struct bwn_phy *phy = &mac->mac_phy;
3666 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
3670 bwn_nphy_stay_in_carrier_search(mac, 1);
3672 tmp = BWN_PHY_READ(mac, BWN_NPHY_SAMP_STAT);
3674 BWN_PHY_SET(mac, BWN_NPHY_SAMP_CMD, BWN_NPHY_SAMP_CMD_STOP);
3676 BWN_PHY_MASK(mac, BWN_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
3678 BWN_PHY_MASK(mac, BWN_NPHY_SAMP_CMD, ~0x0004);
3682 bwn_ntab_write(mac, BWN_NTAB16(15, 87), tmp);
3688 bwn_nphy_rf_ctl_override_rev19(mac, 0x80, 0, 0, true,
3691 bwn_nphy_rf_ctl_override_rev7(mac, 0x80, 0, 0, true, 1);
3696 bwn_nphy_stay_in_carrier_search(mac, 0);
3700 static void bwn_nphy_iq_cal_gain_params(struct bwn_mac *mac, uint16_t core,
3704 struct bwn_phy *phy = &mac->mac_phy;
3708 if (mac->mac_phy.rev >= 3) {
3727 indx = (bwn_current_band(mac) == BWN_BAND_5G) ?
3749 static void bwn_nphy_tx_power_ctrl(struct bwn_mac *mac, bool enable)
3751 struct bwn_phy *phy = &mac->mac_phy;
3752 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
3755 bwn_band_t band = bwn_current_band(mac);
3758 bwn_nphy_stay_in_carrier_search(mac, 1);
3762 if (mac->mac_phy.rev >= 3 &&
3763 (BWN_PHY_READ(mac, BWN_NPHY_TXPCTL_CMD) &
3768 nphy->tx_pwr_idx[0] = BWN_PHY_READ(mac,
3770 nphy->tx_pwr_idx[1] = BWN_PHY_READ(mac,
3774 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, 0x6840);
3776 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, 0);
3778 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, 0x6C40);
3780 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, 0);
3783 if (mac->mac_phy.rev >= 3)
3785 BWN_PHY_MASK(mac, BWN_NPHY_TXPCTL_CMD, ~tmp);
3787 if (mac->mac_phy.rev >= 3) {
3788 BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER1, 0x0100);
3789 BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER, 0x0100);
3791 BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER, 0x4000);
3794 if (mac->mac_phy.rev == 2)
3795 BWN_PHY_SETMASK(mac, BWN_NPHY_BPHY_CTL3,
3797 else if (mac->mac_phy.rev < 2)
3798 BWN_PHY_SETMASK(mac, BWN_NPHY_BPHY_CTL3,
3801 if (mac->mac_phy.rev < 2 && bwn_is_40mhz(mac))
3802 bwn_hf_write(mac, bwn_hf_read(mac) | BWN_HF_TSSI_RESET_PSM_WORKAROUN);
3804 bwn_ntab_write_bulk(mac, BWN_NTAB16(26, 64), 84,
3806 bwn_ntab_write_bulk(mac, BWN_NTAB16(27, 64), 84,
3813 if (mac->mac_phy.rev >= 3) {
3818 BWN_PHY_SETMASK(mac, BWN_NPHY_TXPCTL_CMD, ~(bmask), val);
3824 BWN_PHY_SETMASK(mac, BWN_NPHY_TXPCTL_CMD,
3827 BWN_PHY_SETMASK(mac, BWN_NPHY_TXPCTL_INIT,
3831 BWN_PHY_SETMASK(mac, BWN_NPHY_TXPCTL_CMD,
3835 BWN_PHY_SETMASK(mac,
3842 if (mac->mac_phy.rev >= 3) {
3846 BWN_PHY_SETMASK(mac, BWN_NPHY_TXPCTL_CMD,
3849 if (mac->mac_phy.rev > 1)
3850 BWN_PHY_SETMASK(mac,
3860 if (mac->mac_phy.rev >= 3) {
3861 BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_OVER1, ~0x100);
3862 BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_OVER, ~0x100);
3864 BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_OVER, ~0x4000);
3867 if (mac->mac_phy.rev == 2)
3868 BWN_PHY_SETMASK(mac, BWN_NPHY_BPHY_CTL3, ~0xFF, 0x3b);
3869 else if (mac->mac_phy.rev < 2)
3870 BWN_PHY_SETMASK(mac, BWN_NPHY_BPHY_CTL3, ~0xFF, 0x40);
3872 if (mac->mac_phy.rev < 2 && bwn_is_40mhz(mac))
3873 bwn_hf_write(mac, bwn_hf_read(mac) & ~BWN_HF_TSSI_RESET_PSM_WORKAROUN);
3875 if (bwn_nphy_ipa(mac)) {
3876 BWN_PHY_MASK(mac, BWN_NPHY_PAPD_EN0, ~0x4);
3877 BWN_PHY_MASK(mac, BWN_NPHY_PAPD_EN1, ~0x4);
3882 bwn_nphy_stay_in_carrier_search(mac, 0);
3886 static int bwn_nphy_tx_power_fix(struct bwn_mac *mac)
3888 struct bwn_softc *sc = mac->mac_sc;
3889 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
3893 uint16_t freq = bwn_get_centre_freq(mac);
3898 bwn_nphy_stay_in_carrier_search(mac, 1);
3901 if (mac->mac_phy.rev >= 7) {
3903 } else if (mac->mac_phy.rev >= 3) {
3925 if (bwn_current_band(mac) == BWN_BAND_2G) {
3944 if (mac->mac_phy.rev < 7 &&
3956 const uint32_t *table = bwn_nphy_get_tx_gain_table(mac);
3962 if (mac->mac_phy.rev >= 3)
3967 if (mac->mac_phy.rev >= 7)
3973 if (mac->mac_phy.rev >= 3) {
3975 BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER1, 0x0100);
3977 BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER, 0x0100);
3979 BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER, 0x4000);
3983 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_DACGAIN1, dac_gain);
3985 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_DACGAIN2, dac_gain);
3987 bwn_ntab_write(mac, BWN_NTAB16(0x7, 0x110 + i), radio_gain);
3989 tmp = bwn_ntab_read(mac, BWN_NTAB16(0xF, 0x57));
3994 bwn_ntab_write(mac, BWN_NTAB16(0xF, 0x57), tmp);
3996 if (bwn_nphy_ipa(mac)) {
4000 tmp32 = bwn_ntab_read(mac, BWN_NTAB32(26 + i,
4002 BWN_PHY_SETMASK(mac, reg, 0xE00F, (uint32_t) tmp32 << 4);
4003 BWN_PHY_SET(mac, reg, 0x4);
4007 BWN_PHY_MASK(mac, BWN_NPHY_BPHY_CTL2, ~BWN_NPHY_BPHY_CTL2_LUT);
4010 bwn_nphy_stay_in_carrier_search(mac, 0);
4015 static void bwn_nphy_ipa_internal_tssi_setup(struct bwn_mac *mac)
4017 struct bwn_phy *phy = &mac->mac_phy;
4027 if (bwn_current_band(mac) == BWN_BAND_2G) {
4028 BWN_RF_WRITE(mac, r + 0x5, 0x5);
4029 BWN_RF_WRITE(mac, r + 0x9, 0xE);
4031 BWN_RF_WRITE(mac, r + 0xA, 0);
4033 BWN_RF_WRITE(mac, r + 0xB, 1);
4035 BWN_RF_WRITE(mac, r + 0xB, 0x31);
4037 BWN_RF_WRITE(mac, r + 0x5, 0x9);
4038 BWN_RF_WRITE(mac, r + 0x9, 0xC);
4039 BWN_RF_WRITE(mac, r + 0xB, 0x0);
4041 BWN_RF_WRITE(mac, r + 0xA, 1);
4043 BWN_RF_WRITE(mac, r + 0xA, 0x31);
4045 BWN_RF_WRITE(mac, r + 0x6, 0);
4046 BWN_RF_WRITE(mac, r + 0x7, 0);
4047 BWN_RF_WRITE(mac, r + 0x8, 3);
4048 BWN_RF_WRITE(mac, r + 0xC, 0);
4051 if (bwn_current_band(mac) == BWN_BAND_2G)
4052 BWN_RF_WRITE(mac, B2056_SYN_RESERVED_ADDR31, 0x128);
4054 BWN_RF_WRITE(mac, B2056_SYN_RESERVED_ADDR31, 0x80);
4055 BWN_RF_WRITE(mac, B2056_SYN_RESERVED_ADDR30, 0);
4056 BWN_RF_WRITE(mac, B2056_SYN_GPIO_MASTER1, 0x29);
4061 BWN_RF_WRITE(mac, r | B2056_TX_IQCAL_VCM_HG, 0);
4062 BWN_RF_WRITE(mac, r | B2056_TX_IQCAL_IDAC, 0);
4063 BWN_RF_WRITE(mac, r | B2056_TX_TSSI_VCM, 3);
4064 BWN_RF_WRITE(mac, r | B2056_TX_TX_AMP_DET, 0);
4065 BWN_RF_WRITE(mac, r | B2056_TX_TSSI_MISC1, 8);
4066 BWN_RF_WRITE(mac, r | B2056_TX_TSSI_MISC2, 0);
4067 BWN_RF_WRITE(mac, r | B2056_TX_TSSI_MISC3, 0);
4068 if (bwn_current_band(mac) == BWN_BAND_2G) {
4069 BWN_RF_WRITE(mac, r | B2056_TX_TX_SSI_MASTER,
4072 BWN_RF_WRITE(mac, r | B2056_TX_TSSIA,
4075 BWN_RF_WRITE(mac, r | B2056_TX_TSSIG,
4078 BWN_RF_WRITE(mac, r | B2056_TX_TSSIG,
4080 BWN_RF_WRITE(mac, r | B2056_TX_TX_SSI_MUX,
4083 BWN_RF_WRITE(mac, r | B2056_TX_TX_SSI_MASTER,
4085 BWN_RF_WRITE(mac, r | B2056_TX_TSSIA, 0x31);
4086 BWN_RF_WRITE(mac, r | B2056_TX_TSSIG, 0x0);
4087 BWN_RF_WRITE(mac, r | B2056_TX_TX_SSI_MUX,
4099 static void bwn_nphy_tx_power_ctl_idle_tssi(struct bwn_mac *mac)
4101 struct bwn_phy *phy = &mac->mac_phy;
4102 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
4107 if (bwn_is_chan_passive(mac))
4110 if (bwn_nphy_ipa(mac))
4111 bwn_nphy_ipa_internal_tssi_setup(mac);
4114 bwn_nphy_rf_ctl_override_rev19(mac, 0x1000, 0, 3, false, 0);
4116 bwn_nphy_rf_ctl_override_rev7(mac, 0x1000, 0, 3, false, 0);
4118 bwn_nphy_rf_ctl_override(mac, 0x2000, 0, 3, false);
4120 bwn_nphy_stop_playback(mac);
4121 bwn_nphy_tx_tone(mac, 4000, 0, false, false, false);
4123 tmp = bwn_nphy_poll_rssi(mac, N_RSSI_TSSI_2G, rssi, 1);
4124 bwn_nphy_stop_playback(mac);
4126 bwn_nphy_rssi_select(mac, 0, N_RSSI_W1);
4129 bwn_nphy_rf_ctl_override_rev19(mac, 0x1000, 0, 3, true, 0);
4131 bwn_nphy_rf_ctl_override_rev7(mac, 0x1000, 0, 3, true, 0);
4133 bwn_nphy_rf_ctl_override(mac, 0x2000, 0, 3, true);
4150 static void bwn_nphy_tx_prepare_adjusted_power_table(struct bwn_mac *mac)
4152 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
4178 if (bwn_is_40mhz(mac) && mac->mac_phy.rev >= 5) {
4182 idx = bwn_is_40mhz(mac) ? 52 : 4;
4186 idx = bwn_is_40mhz(mac) ? 76 : 28;
4189 idx = bwn_is_40mhz(mac) ? 84 : 36;
4192 idx = bwn_is_40mhz(mac) ? 92 : 44;
4211 static void bwn_nphy_tx_power_ctl_setup(struct bwn_mac *mac)
4213 struct bwn_softc *sc = mac->mac_sc;
4214 struct bwn_phy *phy = &mac->mac_phy;
4215 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
4226 uint16_t freq = bwn_get_centre_freq(mac);
4233 if (bwn_nphy_get_core_power_info(mac, n,
4235 BWN_ERRPRINTF(mac->mac_sc,
4243 BWN_WRITE_SETMASK4(mac, BWN_MACCTL, ~0, 0x200000);
4244 BWN_READ_4(mac, BWN_MACCTL);
4249 bwn_nphy_stay_in_carrier_search(mac, true);
4251 BWN_PHY_SET(mac, BWN_NPHY_TSSIMODE, BWN_NPHY_TSSIMODE_EN);
4252 if (mac->mac_phy.rev >= 3)
4253 BWN_PHY_MASK(mac, BWN_NPHY_TXPCTL_CMD,
4256 BWN_PHY_SET(mac, BWN_NPHY_TXPCTL_CMD,
4260 BWN_WRITE_SETMASK4(mac, BWN_MACCTL, ~0x200000, 0);
4274 if (bwn_current_band(mac) == BWN_BAND_2G) {
4316 ppr_max = bwn_ppr_get_max(mac, &nphy->tx_pwr_max_ppr);
4322 if (mac->mac_phy.rev >= 3) {
4324 BWN_PHY_SET(mac, BWN_NPHY_TXPCTL_ITSSI, 0x4000);
4325 if (mac->mac_phy.rev >= 7) {
4328 if (bwn_nphy_ipa(mac))
4329 BWN_RF_WRITE(mac, r + 0x9, (bwn_current_band(mac) == BWN_BAND_2G) ? 0xE : 0xC);
4332 if (bwn_nphy_ipa(mac)) {
4333 tmp = (bwn_current_band(mac) == BWN_BAND_5G) ? 0xC : 0xE;
4334 BWN_RF_WRITE(mac,
4336 BWN_RF_WRITE(mac,
4339 BWN_RF_WRITE(mac,
4341 BWN_RF_WRITE(mac,
4348 BWN_WRITE_SETMASK4(mac, BWN_MACCTL, ~0, 0x200000);
4349 BWN_READ_4(mac, BWN_MACCTL);
4356 BWN_PHY_SETMASK(mac, BWN_NPHY_TXPCTL_CMD,
4358 BWN_PHY_SETMASK(mac, BWN_NPHY_TXPCTL_INIT,
4361 BWN_PHY_SETMASK(mac, BWN_NPHY_TXPCTL_CMD,
4363 if (mac->mac_phy.rev > 1)
4364 BWN_PHY_SETMASK(mac, BWN_NPHY_TXPCTL_INIT,
4369 BWN_WRITE_SETMASK4(mac, BWN_MACCTL, ~0x200000, 0);
4371 BWN_PHY_WRITE(mac, BWN_NPHY_TXPCTL_N,
4374 BWN_PHY_WRITE(mac, BWN_NPHY_TXPCTL_ITSSI,
4378 BWN_PHY_WRITE(mac, BWN_NPHY_TXPCTL_TPWR,
4387 if (mac->mac_phy.rev < 3 && (i <= (31 - idle[c] + 1)))
4391 bwn_ntab_write_bulk(mac, BWN_NTAB32(26 + c, 0), 64, regval);
4394 bwn_nphy_tx_prepare_adjusted_power_table(mac);
4395 bwn_ntab_write_bulk(mac, BWN_NTAB16(26, 64), 84, nphy->adj_pwr_tbl);
4396 bwn_ntab_write_bulk(mac, BWN_NTAB16(27, 64), 84, nphy->adj_pwr_tbl);
4399 bwn_nphy_stay_in_carrier_search(mac, false);
4402 static void bwn_nphy_tx_gain_table_upload(struct bwn_mac *mac)
4404 struct bwn_phy *phy = &mac->mac_phy;
4412 table = bwn_nphy_get_tx_gain_table(mac);
4416 bwn_ntab_write_bulk(mac, BWN_NTAB32(26, 192), 128, table);
4417 bwn_ntab_write_bulk(mac, BWN_NTAB32(27, 192), 128, table);
4429 rf_pwr_offset_table = bwn_ntab_get_rf_pwr_offset_table(mac);
4443 if (bwn_current_band(mac) == BWN_BAND_2G)
4449 if (bwn_current_band(mac) == BWN_BAND_2G)
4455 bwn_ntab_write(mac, BWN_NTAB32(26, 576 + i), rfpwr_offset);
4456 bwn_ntab_write(mac, BWN_NTAB32(27, 576 + i), rfpwr_offset);
4461 static void bwn_nphy_pa_override(struct bwn_mac *mac, bool enable)
4463 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
4468 nphy->rfctrl_intc1_save = BWN_PHY_READ(mac,
4470 nphy->rfctrl_intc2_save = BWN_PHY_READ(mac,
4472 band = bwn_current_band(mac);
4473 if (mac->mac_phy.rev >= 7) {
4475 } else if (mac->mac_phy.rev >= 3) {
4486 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC1, tmp);
4487 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC2, tmp);
4489 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC1,
4491 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC2,
4500 static void bwn_nphy_tx_lpf_bw(struct bwn_mac *mac)
4504 if (mac->mac_phy.rev < 3 || mac->mac_phy.rev >= 7)
4507 if (bwn_nphy_ipa(mac))
4508 tmp = bwn_is_40mhz(mac) ? 5 : 4;
4510 tmp = bwn_is_40mhz(mac) ? 3 : 1;
4511 BWN_PHY_WRITE(mac, BWN_NPHY_TXF_40CO_B32S2,
4514 if (bwn_nphy_ipa(mac)) {
4515 tmp = bwn_is_40mhz(mac) ? 4 : 1;
4516 BWN_PHY_WRITE(mac, BWN_NPHY_TXF_40CO_B1S2,
4522 static void bwn_nphy_rx_iq_est(struct bwn_mac *mac, struct bwn_nphy_iq_est *est,
4528 BWN_PHY_WRITE(mac, BWN_NPHY_IQEST_SAMCNT, samps);
4529 BWN_PHY_SETMASK(mac, BWN_NPHY_IQEST_WT, ~BWN_NPHY_IQEST_WT_VAL, time);
4531 BWN_PHY_SET(mac, BWN_NPHY_IQEST_CMD, BWN_NPHY_IQEST_CMD_MODE);
4533 BWN_PHY_MASK(mac, BWN_NPHY_IQEST_CMD, ~BWN_NPHY_IQEST_CMD_MODE);
4535 BWN_PHY_SET(mac, BWN_NPHY_IQEST_CMD, BWN_NPHY_IQEST_CMD_START);
4538 tmp = BWN_PHY_READ(mac, BWN_NPHY_IQEST_CMD);
4540 est->i0_pwr = (BWN_PHY_READ(mac, BWN_NPHY_IQEST_IPACC_HI0) << 16) |
4541 BWN_PHY_READ(mac, BWN_NPHY_IQEST_IPACC_LO0);
4542 est->q0_pwr = (BWN_PHY_READ(mac, BWN_NPHY_IQEST_QPACC_HI0) << 16) |
4543 BWN_PHY_READ(mac, BWN_NPHY_IQEST_QPACC_LO0);
4544 est->iq0_prod = (BWN_PHY_READ(mac, BWN_NPHY_IQEST_IQACC_HI0) << 16) |
4545 BWN_PHY_READ(mac, BWN_NPHY_IQEST_IQACC_LO0);
4547 est->i1_pwr = (BWN_PHY_READ(mac, BWN_NPHY_IQEST_IPACC_HI1) << 16) |
4548 BWN_PHY_READ(mac, BWN_NPHY_IQEST_IPACC_LO1);
4549 est->q1_pwr = (BWN_PHY_READ(mac, BWN_NPHY_IQEST_QPACC_HI1) << 16) |
4550 BWN_PHY_READ(mac, BWN_NPHY_IQEST_QPACC_LO1);
4551 est->iq1_prod = (BWN_PHY_READ(mac, BWN_NPHY_IQEST_IQACC_HI1) << 16) |
4552 BWN_PHY_READ(mac, BWN_NPHY_IQEST_IQACC_LO1);
4561 static void bwn_nphy_rx_iq_coeffs(struct bwn_mac *mac, bool write,
4565 BWN_PHY_WRITE(mac, BWN_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
4566 BWN_PHY_WRITE(mac, BWN_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
4567 BWN_PHY_WRITE(mac, BWN_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
4568 BWN_PHY_WRITE(mac, BWN_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
4570 pcomp->a0 = BWN_PHY_READ(mac, BWN_NPHY_C1_RXIQ_COMPA0);
4571 pcomp->b0 = BWN_PHY_READ(mac, BWN_NPHY_C1_RXIQ_COMPB0);
4572 pcomp->a1 = BWN_PHY_READ(mac, BWN_NPHY_C2_RXIQ_COMPA1);
4573 pcomp->b1 = BWN_PHY_READ(mac, BWN_NPHY_C2_RXIQ_COMPB1);
4580 static void bwn_nphy_rx_cal_phy_cleanup(struct bwn_mac *mac, uint8_t core)
4582 uint16_t *regs = mac->mac_phy.phy_n->tx_rx_cal_phy_saveregs;
4584 BWN_PHY_WRITE(mac, BWN_NPHY_RFSEQCA, regs[0]);
4586 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C1, regs[1]);
4587 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER1, regs[2]);
4589 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C2, regs[1]);
4590 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, regs[2]);
4592 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC1, regs[3]);
4593 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC2, regs[4]);
4594 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_RSSIO1, regs[5]);
4595 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_RSSIO2, regs[6]);
4596 BWN_PHY_WRITE(mac, BWN_NPHY_TXF_40CO_B1S1, regs[7]);
4597 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_OVER, regs[8]);
4598 BWN_PHY_WRITE(mac, BWN_NPHY_PAPD_EN0, regs[9]);
4599 BWN_PHY_WRITE(mac, BWN_NPHY_PAPD_EN1, regs[10]);
4603 static void bwn_nphy_rx_cal_phy_setup(struct bwn_mac *mac, uint8_t core)
4606 uint16_t *regs = mac->mac_phy.phy_n->tx_rx_cal_phy_saveregs;
4608 regs[0] = BWN_PHY_READ(mac, BWN_NPHY_RFSEQCA);
4610 regs[1] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_C1);
4611 regs[2] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_OVER1);
4613 regs[1] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_C2);
4614 regs[2] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_OVER);
4616 regs[3] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_INTC1);
4617 regs[4] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_INTC2);
4618 regs[5] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_RSSIO1);
4619 regs[6] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_RSSIO2);
4620 regs[7] = BWN_PHY_READ(mac, BWN_NPHY_TXF_40CO_B1S1);
4621 regs[8] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_OVER);
4622 regs[9] = BWN_PHY_READ(mac, BWN_NPHY_PAPD_EN0);
4623 regs[10] = BWN_PHY_READ(mac, BWN_NPHY_PAPD_EN1);
4625 BWN_PHY_MASK(mac, BWN_NPHY_PAPD_EN0, ~0x0001);
4626 BWN_PHY_MASK(mac, BWN_NPHY_PAPD_EN1, ~0x0001);
4628 BWN_PHY_SETMASK(mac, BWN_NPHY_RFSEQCA,
4631 BWN_PHY_SETMASK(mac, BWN_NPHY_RFSEQCA, ~BWN_NPHY_RFSEQCA_TXEN,
4633 BWN_PHY_SETMASK(mac, BWN_NPHY_RFSEQCA, ~BWN_NPHY_RFSEQCA_RXEN,
4635 BWN_PHY_SETMASK(mac, BWN_NPHY_RFSEQCA, ~BWN_NPHY_RFSEQCA_TXDIS,
4639 BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_C1, ~0x0007);
4640 BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER1, 0x0007);
4642 BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_C2, ~0x0007);
4643 BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER, 0x0007);
4646 bwn_nphy_rf_ctl_intc_override(mac, N_INTC_OVERRIDE_PA, 0, 3);
4647 bwn_nphy_rf_ctl_override(mac, 8, 0, 3, false);
4648 bwn_nphy_force_rf_sequence(mac, BWN_RFSEQ_RX2TX);
4657 bwn_nphy_rf_ctl_intc_override(mac, N_INTC_OVERRIDE_TRSW, rxval,
4659 bwn_nphy_rf_ctl_intc_override(mac, N_INTC_OVERRIDE_TRSW, txval,
4665 static void bwn_nphy_calc_rx_iq_comp(struct bwn_mac *mac, uint8_t mask)
4683 bwn_nphy_rx_iq_coeffs(mac, false, &old);
4684 bwn_nphy_rx_iq_coeffs(mac, true, &new);
4685 bwn_nphy_rx_iq_est(mac, &est, 0x4000, 32, false);
4735 b = bwn_sqrt(mac, b / tmp - a * a) - (1 << 10);
4738 if (mac->mac_phy.rev >= 3) {
4746 if (mac->mac_phy.rev >= 3) {
4759 bwn_nphy_rx_iq_coeffs(mac, true, &new);
4763 static void bwn_nphy_tx_iq_workaround(struct bwn_mac *mac)
4766 bwn_ntab_read_bulk(mac, BWN_NTAB16(0xF, 0x50), 4, array);
4768 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHM_SH_NPHY_TXIQW0, array[0]);
4769 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHM_SH_NPHY_TXIQW1, array[1]);
4770 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHM_SH_NPHY_TXIQW2, array[2]);
4771 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHM_SH_NPHY_TXIQW3, array[3]);
4775 static void bwn_nphy_spur_workaround(struct bwn_mac *mac)
4777 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
4779 uint8_t channel = bwn_get_chan(mac);
4783 if (mac->mac_phy.rev < 3) {
4784 BWN_ERRPRINTF(mac->mac_sc, "%s: phy rev %d out of range\n",
4786 mac->mac_phy.rev);
4790 bwn_nphy_stay_in_carrier_search(mac, 1);
4794 if (channel == 11 && bwn_is_40mhz(mac))
4834 bwn_nphy_stay_in_carrier_search(mac, 0);
4838 static void bwn_nphy_tx_pwr_ctrl_coef_setup(struct bwn_mac *mac)
4840 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
4848 bwn_nphy_stay_in_carrier_search(mac, true);
4850 bwn_ntab_read_bulk(mac, BWN_NTAB16(15, 80), 7, buffer);
4855 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR,
4858 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATAHI,
4860 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO,
4869 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR,
4872 if (mac->mac_phy.rev >= 3) {
4879 if (mac->mac_phy.rev < 3) {
4885 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATAHI,
4887 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO,
4892 if (mac->mac_phy.rev >= 3) {
4893 bwn_shm_write_2(mac, BWN_SHARED,
4895 bwn_shm_write_2(mac, BWN_SHARED,
4900 bwn_nphy_stay_in_carrier_search(mac, false);
4907 static void bwn_nphy_restore_rssi_cal(struct bwn_mac *mac)
4909 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
4914 if (bwn_current_band(mac) == BWN_BAND_2G) {
4926 if (mac->mac_phy.rev >= 19) {
4928 } else if (mac->mac_phy.rev >= 7) {
4929 BWN_RF_SETMASK(mac, R2057_NB_MASTER_CORE0, ~R2057_VCM_MASK,
4931 BWN_RF_SETMASK(mac, R2057_NB_MASTER_CORE1, ~R2057_VCM_MASK,
4934 BWN_RF_SETMASK(mac, B2056_RX0 | B2056_RX_RSSI_MISC, 0xE3,
4936 BWN_RF_SETMASK(mac, B2056_RX1 | B2056_RX_RSSI_MISC, 0xE3,
4940 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
4941 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
4942 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
4943 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
4945 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
4946 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
4947 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
4948 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
4950 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
4951 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
4952 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
4953 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
4956 static void bwn_nphy_tx_cal_radio_setup_rev19(struct bwn_mac *mac)
4961 static void bwn_nphy_tx_cal_radio_setup_rev7(struct bwn_mac *mac)
4963 struct bwn_phy *phy = &mac->mac_phy;
4964 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
4973 save[off + 0] = BWN_RF_READ(mac, r + R2057_TX0_TX_SSI_MASTER);
4974 save[off + 1] = BWN_RF_READ(mac, r + R2057_TX0_IQCAL_VCM_HG);
4975 save[off + 2] = BWN_RF_READ(mac, r + R2057_TX0_IQCAL_IDAC);
4976 save[off + 3] = BWN_RF_READ(mac, r + R2057_TX0_TSSI_VCM);
4978 save[off + 5] = BWN_RF_READ(mac, r + R2057_TX0_TX_SSI_MUX);
4980 save[off + 6] = BWN_RF_READ(mac, r + R2057_TX0_TSSIA);
4981 save[off + 7] = BWN_RF_READ(mac, r + R2057_TX0_TSSIG);
4982 save[off + 8] = BWN_RF_READ(mac, r + R2057_TX0_TSSI_MISC1);
4984 if (bwn_current_band(mac) == BWN_BAND_5G) {
4985 BWN_RF_WRITE(mac, r + R2057_TX0_TX_SSI_MASTER, 0xA);
4986 BWN_RF_WRITE(mac, r + R2057_TX0_IQCAL_VCM_HG, 0x43);
4987 BWN_RF_WRITE(mac, r + R2057_TX0_IQCAL_IDAC, 0x55);
4988 BWN_RF_WRITE(mac, r + R2057_TX0_TSSI_VCM, 0);
4989 BWN_RF_WRITE(mac, r + R2057_TX0_TSSIG, 0);
4991 BWN_RF_WRITE(mac, r + R2057_TX0_TX_SSI_MUX, 0x4);
4993 BWN_RF_WRITE(mac, r + R2057_TX0_TSSIA, tmp);
4995 BWN_RF_WRITE(mac, r + R2057_TX0_TSSI_MISC1, 0x00);
4997 BWN_RF_WRITE(mac, r + R2057_TX0_TX_SSI_MASTER, 0x6);
4998 BWN_RF_WRITE(mac, r + R2057_TX0_IQCAL_VCM_HG, 0x43);
4999 BWN_RF_WRITE(mac, r + R2057_TX0_IQCAL_IDAC, 0x55);
5000 BWN_RF_WRITE(mac, r + R2057_TX0_TSSI_VCM, 0);
5003 BWN_RF_WRITE(mac, r + R2057_TX0_TSSIA, 0);
5005 BWN_RF_WRITE(mac, r + R2057_TX0_TX_SSI_MUX, 0x6);
5007 BWN_RF_WRITE(mac, r + R2057_TX0_TSSIG, tmp);
5009 BWN_RF_WRITE(mac, r + R2057_TX0_TSSI_MISC1, 0);
5015 static void bwn_nphy_tx_cal_radio_setup(struct bwn_mac *mac)
5017 struct bwn_phy *phy = &mac->mac_phy;
5018 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
5024 bwn_nphy_tx_cal_radio_setup_rev19(mac);
5026 bwn_nphy_tx_cal_radio_setup_rev7(mac);
5032 save[offset + 0] = BWN_RF_READ(mac, B2055_CAL_RVARCTL);
5033 save[offset + 1] = BWN_RF_READ(mac, B2055_CAL_LPOCTL);
5034 save[offset + 2] = BWN_RF_READ(mac, B2055_CAL_TS);
5035 save[offset + 3] = BWN_RF_READ(mac, B2055_CAL_RCCALRTS);
5036 save[offset + 4] = BWN_RF_READ(mac, B2055_CAL_RCALRTS);
5037 save[offset + 5] = BWN_RF_READ(mac, B2055_PADDRV);
5038 save[offset + 6] = BWN_RF_READ(mac, B2055_XOCTL1);
5039 save[offset + 7] = BWN_RF_READ(mac, B2055_XOCTL2);
5040 save[offset + 8] = BWN_RF_READ(mac, B2055_XOREGUL);
5041 save[offset + 9] = BWN_RF_READ(mac, B2055_XOMISC);
5042 save[offset + 10] = BWN_RF_READ(mac, B2055_PLL_LFC1);
5044 if (bwn_current_band(mac) == BWN_BAND_5G) {
5045 BWN_RF_WRITE(mac, tmp | B2055_CAL_RVARCTL, 0x0A);
5046 BWN_RF_WRITE(mac, tmp | B2055_CAL_LPOCTL, 0x40);
5047 BWN_RF_WRITE(mac, tmp | B2055_CAL_TS, 0x55);
5048 BWN_RF_WRITE(mac, tmp | B2055_CAL_RCCALRTS, 0);
5049 BWN_RF_WRITE(mac, tmp | B2055_CAL_RCALRTS, 0);
5051 BWN_RF_WRITE(mac, tmp | B2055_PADDRV, 4);
5052 BWN_RF_WRITE(mac, tmp | B2055_XOCTL1, 1);
5054 BWN_RF_WRITE(mac, tmp | B2055_PADDRV, 0);
5055 BWN_RF_WRITE(mac, tmp | B2055_XOCTL1, 0x2F);
5057 BWN_RF_WRITE(mac, tmp | B2055_XOCTL2, 0);
5059 BWN_RF_WRITE(mac, tmp | B2055_CAL_RVARCTL, 0x06);
5060 BWN_RF_WRITE(mac, tmp | B2055_CAL_LPOCTL, 0x40);
5061 BWN_RF_WRITE(mac, tmp | B2055_CAL_TS, 0x55);
5062 BWN_RF_WRITE(mac, tmp | B2055_CAL_RCCALRTS, 0);
5063 BWN_RF_WRITE(mac, tmp | B2055_CAL_RCALRTS, 0);
5064 BWN_RF_WRITE(mac, tmp | B2055_XOCTL1, 0);
5066 BWN_RF_WRITE(mac, tmp | B2055_PADDRV, 6);
5067 BWN_RF_WRITE(mac, tmp | B2055_XOCTL2,
5068 (mac->mac_phy.rev < 5) ? 0x11 : 0x01);
5070 BWN_RF_WRITE(mac, tmp | B2055_PADDRV, 0);
5071 BWN_RF_WRITE(mac, tmp | B2055_XOCTL2, 0);
5074 BWN_RF_WRITE(mac, tmp | B2055_XOREGUL, 0);
5075 BWN_RF_WRITE(mac, tmp | B2055_XOMISC, 0);
5076 BWN_RF_WRITE(mac, tmp | B2055_PLL_LFC1, 0);
5079 save[0] = BWN_RF_READ(mac, B2055_C1_TX_RF_IQCAL1);
5080 BWN_RF_WRITE(mac, B2055_C1_TX_RF_IQCAL1, 0x29);
5082 save[1] = BWN_RF_READ(mac, B2055_C1_TX_RF_IQCAL2);
5083 BWN_RF_WRITE(mac, B2055_C1_TX_RF_IQCAL2, 0x54);
5085 save[2] = BWN_RF_READ(mac, B2055_C2_TX_RF_IQCAL1);
5086 BWN_RF_WRITE(mac, B2055_C2_TX_RF_IQCAL1, 0x29);
5088 save[3] = BWN_RF_READ(mac, B2055_C2_TX_RF_IQCAL2);
5089 BWN_RF_WRITE(mac, B2055_C2_TX_RF_IQCAL2, 0x54);
5091 save[3] = BWN_RF_READ(mac, B2055_C1_PWRDET_RXTX);
5092 save[4] = BWN_RF_READ(mac, B2055_C2_PWRDET_RXTX);
5094 if (!(BWN_PHY_READ(mac, BWN_NPHY_BANDCTL) &
5096 BWN_RF_WRITE(mac, B2055_C1_PWRDET_RXTX, 0x04);
5097 BWN_RF_WRITE(mac, B2055_C2_PWRDET_RXTX, 0x04);
5099 BWN_RF_WRITE(mac, B2055_C1_PWRDET_RXTX, 0x20);
5100 BWN_RF_WRITE(mac, B2055_C2_PWRDET_RXTX, 0x20);
5103 if (mac->mac_phy.rev < 2) {
5104 BWN_RF_SET(mac, B2055_C1_TX_BB_MXGM, 0x20);
5105 BWN_RF_SET(mac, B2055_C2_TX_BB_MXGM, 0x20);
5107 BWN_RF_MASK(mac, B2055_C1_TX_BB_MXGM, ~0x20);
5108 BWN_RF_MASK(mac, B2055_C2_TX_BB_MXGM, ~0x20);
5114 static void bwn_nphy_update_tx_cal_ladder(struct bwn_mac *mac, uint16_t core)
5116 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
5128 bwn_ntab_write(mac, BWN_NTAB16(15, i), entry);
5132 bwn_ntab_write(mac, BWN_NTAB16(15, i + 32), entry);
5136 static void bwn_nphy_pa_set_tx_dig_filter(struct bwn_mac *mac, uint16_t offset,
5144 BWN_PHY_WRITE(mac, offset, filter[i]);
5148 static void bwn_nphy_ext_pa_set_tx_dig_filters(struct bwn_mac *mac)
5150 bwn_nphy_pa_set_tx_dig_filter(mac, 0x2C5,
5155 static void bwn_nphy_int_pa_set_tx_dig_filters(struct bwn_mac *mac)
5167 bwn_nphy_pa_set_tx_dig_filter(mac, offset[i],
5171 if (mac->mac_phy.rev == 16)
5172 bwn_nphy_pa_set_tx_dig_filter(mac, 0x186, dig_filter_phy_rev16);
5175 if (mac->mac_phy.rev == 17) {
5176 bwn_nphy_pa_set_tx_dig_filter(mac, 0x186, dig_filter_phy_rev16);
5177 bwn_nphy_pa_set_tx_dig_filter(mac, 0x195,
5181 if (bwn_is_40mhz(mac)) {
5182 bwn_nphy_pa_set_tx_dig_filter(mac, 0x186,
5185 if (bwn_current_band(mac) == BWN_BAND_5G)
5186 bwn_nphy_pa_set_tx_dig_filter(mac, 0x186,
5188 if (bwn_get_chan(mac) == 14)
5189 bwn_nphy_pa_set_tx_dig_filter(mac, 0x186,
5195 static struct bwn_nphy_txgains bwn_nphy_get_tx_gains(struct bwn_mac *mac)
5197 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
5207 bwn_nphy_stay_in_carrier_search(mac, true);
5208 bwn_ntab_read_bulk(mac, BWN_NTAB16(7, 0x110), 2, curr_gain);
5210 bwn_nphy_stay_in_carrier_search(mac, false);
5213 if (mac->mac_phy.rev >= 7) {
5219 } else if (mac->mac_phy.rev >= 3) {
5234 index[0] = (BWN_PHY_READ(mac, BWN_NPHY_C1_TXPCTL_STAT) &
5237 index[1] = (BWN_PHY_READ(mac, BWN_NPHY_C2_TXPCTL_STAT) &
5242 table = bwn_nphy_get_tx_gain_table(mac);
5246 if (mac->mac_phy.rev >= 7) {
5252 } else if (mac->mac_phy.rev >= 3) {
5270 static void bwn_nphy_tx_cal_phy_cleanup(struct bwn_mac *mac)
5272 uint16_t *regs = mac->mac_phy.phy_n->tx_rx_cal_phy_saveregs;
5274 if (mac->mac_phy.rev >= 3) {
5275 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C1, regs[0]);
5276 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C2, regs[1]);
5277 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER1, regs[2]);
5278 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, regs[3]);
5279 BWN_PHY_WRITE(mac, BWN_NPHY_BBCFG, regs[4]);
5280 bwn_ntab_write(mac, BWN_NTAB16(8, 3), regs[5]);
5281 bwn_ntab_write(mac, BWN_NTAB16(8, 19), regs[6]);
5282 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC1, regs[7]);
5283 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC2, regs[8]);
5284 BWN_PHY_WRITE(mac, BWN_NPHY_PAPD_EN0, regs[9]);
5285 BWN_PHY_WRITE(mac, BWN_NPHY_PAPD_EN1, regs[10]);
5286 bwn_nphy_reset_cca(mac);
5288 BWN_PHY_SETMASK(mac, BWN_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
5289 BWN_PHY_SETMASK(mac, BWN_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
5290 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, regs[2]);
5291 bwn_ntab_write(mac, BWN_NTAB16(8, 2), regs[3]);
5292 bwn_ntab_write(mac, BWN_NTAB16(8, 18), regs[4]);
5293 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC1, regs[5]);
5294 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC2, regs[6]);
5299 static void bwn_nphy_tx_cal_phy_setup(struct bwn_mac *mac)
5301 struct bwn_phy *phy = &mac->mac_phy;
5302 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
5303 uint16_t *regs = mac->mac_phy.phy_n->tx_rx_cal_phy_saveregs;
5306 regs[0] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_C1);
5307 regs[1] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_C2);
5308 if (mac->mac_phy.rev >= 3) {
5309 BWN_PHY_SETMASK(mac, BWN_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
5310 BWN_PHY_SETMASK(mac, BWN_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
5312 tmp = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_OVER1);
5314 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER1, tmp | 0x0600);
5316 tmp = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_OVER);
5318 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, tmp | 0x0600);
5320 regs[4] = BWN_PHY_READ(mac, BWN_NPHY_BBCFG);
5321 BWN_PHY_MASK(mac, BWN_NPHY_BBCFG,
5324 tmp = bwn_ntab_read(mac, BWN_NTAB16(8, 3));
5326 bwn_ntab_write(mac, BWN_NTAB16(8, 3), 0);
5328 tmp = bwn_ntab_read(mac, BWN_NTAB16(8, 19));
5330 bwn_ntab_write(mac, BWN_NTAB16(8, 19), 0);
5331 regs[7] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_INTC1);
5332 regs[8] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_INTC2);
5335 bwn_nphy_rf_ctl_intc_override(mac, N_INTC_OVERRIDE_PA,
5338 bwn_nphy_rf_ctl_intc_override(mac, N_INTC_OVERRIDE_PA,
5340 bwn_nphy_rf_ctl_intc_override(mac, N_INTC_OVERRIDE_TRSW, 2, 1);
5341 bwn_nphy_rf_ctl_intc_override(mac, N_INTC_OVERRIDE_TRSW, 8, 2);
5343 regs[9] = BWN_PHY_READ(mac, BWN_NPHY_PAPD_EN0);
5344 regs[10] = BWN_PHY_READ(mac, BWN_NPHY_PAPD_EN1);
5345 BWN_PHY_MASK(mac, BWN_NPHY_PAPD_EN0, ~0x0001);
5346 BWN_PHY_MASK(mac, BWN_NPHY_PAPD_EN1, ~0x0001);
5348 tmp = bwn_nphy_read_lpf_ctl(mac, 0);
5350 bwn_nphy_rf_ctl_override_rev19(mac, 0x80, tmp, 0, false,
5353 bwn_nphy_rf_ctl_override_rev7(mac, 0x80, tmp, 0, false,
5358 bwn_nphy_rf_ctl_override_rev19(mac, 0x8, 0, 0x3,
5361 bwn_nphy_rf_ctl_override_rev7(mac, 0x8, 0, 0x3,
5364 BWN_RF_SETMASK(mac, R2057_OVR_REG0, 1 << 4, 1 << 4);
5365 if (bwn_current_band(mac) == BWN_BAND_2G) {
5366 BWN_RF_SETMASK(mac, R2057_PAD2G_TUNE_PUS_CORE0, ~1, 0);
5367 BWN_RF_SETMASK(mac, R2057_PAD2G_TUNE_PUS_CORE1, ~1, 0);
5369 BWN_RF_SETMASK(mac, R2057_IPA5G_CASCOFFV_PU_CORE0, ~1, 0);
5370 BWN_RF_SETMASK(mac, R2057_IPA5G_CASCOFFV_PU_CORE1, ~1, 0);
5375 BWN_PHY_SETMASK(mac, BWN_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
5376 BWN_PHY_SETMASK(mac, BWN_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
5377 tmp = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_OVER);
5379 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, tmp | 0x3000);
5380 tmp = bwn_ntab_read(mac, BWN_NTAB16(8, 2));
5383 bwn_ntab_write(mac, BWN_NTAB16(8, 2), tmp);
5384 tmp = bwn_ntab_read(mac, BWN_NTAB16(8, 18));
5387 bwn_ntab_write(mac, BWN_NTAB16(8, 18), tmp);
5388 regs[5] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_INTC1);
5389 regs[6] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_INTC2);
5390 if (bwn_current_band(mac) == BWN_BAND_5G)
5394 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC1, tmp);
5395 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC2, tmp);
5400 static void bwn_nphy_save_cal(struct bwn_mac *mac)
5402 struct bwn_phy *phy = &mac->mac_phy;
5403 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
5411 bwn_nphy_stay_in_carrier_search(mac, 1);
5413 if (bwn_current_band(mac) == BWN_BAND_2G) {
5425 bwn_nphy_rx_iq_coeffs(mac, false, rxcal_coeffs);
5430 txcal_radio_regs[0] = BWN_RF_READ(mac,
5432 txcal_radio_regs[1] = BWN_RF_READ(mac,
5434 txcal_radio_regs[4] = BWN_RF_READ(mac,
5436 txcal_radio_regs[5] = BWN_RF_READ(mac,
5438 txcal_radio_regs[2] = BWN_RF_READ(mac,
5440 txcal_radio_regs[3] = BWN_RF_READ(mac,
5442 txcal_radio_regs[6] = BWN_RF_READ(mac,
5444 txcal_radio_regs[7] = BWN_RF_READ(mac,
5447 txcal_radio_regs[0] = BWN_RF_READ(mac, 0x2021);
5448 txcal_radio_regs[1] = BWN_RF_READ(mac, 0x2022);
5449 txcal_radio_regs[2] = BWN_RF_READ(mac, 0x3021);
5450 txcal_radio_regs[3] = BWN_RF_READ(mac, 0x3022);
5451 txcal_radio_regs[4] = BWN_RF_READ(mac, 0x2023);
5452 txcal_radio_regs[5] = BWN_RF_READ(mac, 0x2024);
5453 txcal_radio_regs[6] = BWN_RF_READ(mac, 0x3023);
5454 txcal_radio_regs[7] = BWN_RF_READ(mac, 0x3024);
5456 txcal_radio_regs[0] = BWN_RF_READ(mac, 0x8B);
5457 txcal_radio_regs[1] = BWN_RF_READ(mac, 0xBA);
5458 txcal_radio_regs[2] = BWN_RF_READ(mac, 0x8D);
5459 txcal_radio_regs[3] = BWN_RF_READ(mac, 0xBC);
5461 iqcal_chanspec->center_freq = bwn_get_centre_freq(mac);
5462 iqcal_chanspec->channel_type = bwn_get_chan_type(mac, NULL);
5463 bwn_ntab_read_bulk(mac, BWN_NTAB16(15, 80), 8, table);
5466 bwn_nphy_stay_in_carrier_search(mac, 0);
5470 static void bwn_nphy_restore_cal(struct bwn_mac *mac)
5472 struct bwn_phy *phy = &mac->mac_phy;
5473 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
5483 if (bwn_current_band(mac) == BWN_BAND_2G) {
5495 bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 80), 4, table);
5498 if (mac->mac_phy.rev >= 3)
5504 bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 88), 4, coef);
5505 bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 85), 2, loft);
5506 bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 93), 2, loft);
5508 if (mac->mac_phy.rev < 2)
5509 bwn_nphy_tx_iq_workaround(mac);
5511 if (bwn_current_band(mac) == BWN_BAND_2G) {
5523 BWN_RF_WRITE(mac, R2057_TX0_LOFT_FINE_I,
5525 BWN_RF_WRITE(mac, R2057_TX0_LOFT_FINE_Q,
5527 BWN_RF_WRITE(mac, R2057_TX0_LOFT_COARSE_I,
5529 BWN_RF_WRITE(mac, R2057_TX0_LOFT_COARSE_Q,
5531 BWN_RF_WRITE(mac, R2057_TX1_LOFT_FINE_I,
5533 BWN_RF_WRITE(mac, R2057_TX1_LOFT_FINE_Q,
5535 BWN_RF_WRITE(mac, R2057_TX1_LOFT_COARSE_I,
5537 BWN_RF_WRITE(mac, R2057_TX1_LOFT_COARSE_Q,
5540 BWN_RF_WRITE(mac, 0x2021, txcal_radio_regs[0]);
5541 BWN_RF_WRITE(mac, 0x2022, txcal_radio_regs[1]);
5542 BWN_RF_WRITE(mac, 0x3021, txcal_radio_regs[2]);
5543 BWN_RF_WRITE(mac, 0x3022, txcal_radio_regs[3]);
5544 BWN_RF_WRITE(mac, 0x2023, txcal_radio_regs[4]);
5545 BWN_RF_WRITE(mac, 0x2024, txcal_radio_regs[5]);
5546 BWN_RF_WRITE(mac, 0x3023, txcal_radio_regs[6]);
5547 BWN_RF_WRITE(mac, 0x3024, txcal_radio_regs[7]);
5549 BWN_RF_WRITE(mac, 0x8B, txcal_radio_regs[0]);
5550 BWN_RF_WRITE(mac, 0xBA, txcal_radio_regs[1]);
5551 BWN_RF_WRITE(mac, 0x8D, txcal_radio_regs[2]);
5552 BWN_RF_WRITE(mac, 0xBC, txcal_radio_regs[3]);
5554 bwn_nphy_rx_iq_coeffs(mac, true, rxcal_coeffs);
5558 static int bwn_nphy_cal_tx_iq_lo(struct bwn_mac *mac,
5562 struct bwn_phy *phy = &mac->mac_phy;
5563 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
5580 bwn_nphy_stay_in_carrier_search(mac, true);
5582 if (mac->mac_phy.rev >= 4) {
5587 bwn_ntab_read_bulk(mac, BWN_NTAB16(7, 0x110), 2, save);
5590 bwn_nphy_iq_cal_gain_params(mac, i, target, ¶ms[i]);
5594 bwn_ntab_write_bulk(mac, BWN_NTAB16(7, 0x110), 2, gain);
5596 bwn_nphy_tx_cal_radio_setup(mac);
5597 bwn_nphy_tx_cal_phy_setup(mac);
5599 phy6or5x = mac->mac_phy.rev >= 6 ||
5600 (mac->mac_phy.rev == 5 && nphy->ipa2g_on &&
5601 bwn_current_band(mac) == BWN_BAND_2G);
5603 if (bwn_is_40mhz(mac)) {
5604 bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 0), 18,
5606 bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 32), 18,
5609 bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 0), 18,
5611 bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 32), 18,
5619 BWN_PHY_WRITE(mac, BWN_NPHY_IQLOCAL_CMDGCTL, 0x8AD9);
5621 BWN_PHY_WRITE(mac, BWN_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
5624 if (!bwn_is_40mhz(mac))
5630 bwn_nphy_run_samples(mac, (bwn_is_40mhz(mac) ? 40 : 20) * 8,
5633 error = bwn_nphy_tx_tone(mac, freq, 250, true, false, false);
5639 if (mac->mac_phy.rev < 3)
5645 if (mac->mac_phy.rev < 3)
5649 if (mac->mac_phy.rev >= 3) {
5659 bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 64), length, table);
5662 if (mac->mac_phy.rev >= 3)
5667 if (mac->mac_phy.rev >= 3)
5684 if (mac->mac_phy.rev >= 3)
5689 if (mac->mac_phy.rev >= 3)
5699 bwn_nphy_update_tx_cal_ladder(mac, core);
5704 BWN_PHY_WRITE(mac, BWN_NPHY_IQLOCAL_CMDNNUM, tmp);
5707 buffer[0] = bwn_ntab_read(mac,
5711 bwn_ntab_write(mac, BWN_NTAB16(15, 69 + core),
5715 BWN_PHY_WRITE(mac, BWN_NPHY_IQLOCAL_CMD, cmd);
5717 tmp = BWN_PHY_READ(mac, BWN_NPHY_IQLOCAL_CMD);
5723 bwn_ntab_read_bulk(mac, BWN_NTAB16(15, 96), length,
5725 bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 64), length,
5735 last = (mac->mac_phy.rev < 3) ? 6 : 7;
5738 bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 96), 4, buffer);
5739 bwn_ntab_read_bulk(mac, BWN_NTAB16(15, 80), 4, buffer);
5740 if (mac->mac_phy.rev < 3) {
5746 bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 88), 4,
5748 bwn_ntab_read_bulk(mac, BWN_NTAB16(15, 101), 2,
5750 bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 85), 2,
5752 bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 93), 2,
5755 if (mac->mac_phy.rev < 3)
5757 bwn_ntab_read_bulk(mac, BWN_NTAB16(15, 96), length,
5761 bwn_get_centre_freq(mac);
5762 nphy->txiqlocal_chanspec.channel_type = bwn_get_chan_type(mac, NULL);
5765 if (mac->mac_phy.rev < 3)
5767 bwn_ntab_read_bulk(mac, BWN_NTAB16(15, 96), length,
5771 bwn_nphy_stop_playback(mac);
5772 BWN_PHY_WRITE(mac, BWN_NPHY_IQLOCAL_CMDGCTL, 0);
5775 bwn_nphy_tx_cal_phy_cleanup(mac);
5776 bwn_ntab_write_bulk(mac, BWN_NTAB16(7, 0x110), 2, save);
5778 if (mac->mac_phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
5779 bwn_nphy_tx_iq_workaround(mac);
5781 if (mac->mac_phy.rev >= 4)
5784 bwn_nphy_stay_in_carrier_search(mac, false);
5790 static void bwn_nphy_reapply_tx_cal_coeffs(struct bwn_mac *mac)
5792 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
5798 nphy->txiqlocal_chanspec.center_freq != bwn_get_centre_freq(mac) ||
5799 nphy->txiqlocal_chanspec.channel_type != bwn_get_chan_type(mac, NULL))
5802 bwn_ntab_read_bulk(mac, BWN_NTAB16(15, 80), 7, buffer);
5811 bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 80), 4,
5815 bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 88), 4,
5817 bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 85), 2,
5819 bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 93), 2,
5825 static int bwn_nphy_rev2_cal_rx_iq(struct bwn_mac *mac,
5828 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
5851 bwn_nphy_stay_in_carrier_search(mac, 1);
5853 if (mac->mac_phy.rev < 2)
5854 bwn_nphy_reapply_tx_cal_coeffs(mac);
5855 bwn_ntab_read_bulk(mac, BWN_NTAB16(7, 0x110), 2, gain_save);
5857 bwn_nphy_iq_cal_gain_params(mac, i, target, &cal_params[i]);
5860 bwn_ntab_write_bulk(mac, BWN_NTAB16(7, 0x110), 2, cal_gain);
5873 tmp[1] = BWN_PHY_READ(mac, BWN_NPHY_RFSEQCA);
5874 tmp[2] = BWN_PHY_READ(mac, afectl_core);
5875 tmp[3] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_OVER);
5876 tmp[4] = BWN_PHY_READ(mac, rfctl[0]);
5877 tmp[5] = BWN_PHY_READ(mac, rfctl[1]);
5879 BWN_PHY_SETMASK(mac, BWN_NPHY_RFSEQCA,
5882 BWN_PHY_SETMASK(mac, BWN_NPHY_RFSEQCA, ~BWN_NPHY_RFSEQCA_TXEN,
5884 BWN_PHY_SET(mac, afectl_core, 0x0006);
5885 BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER, 0x0006);
5887 band = bwn_current_band(mac);
5891 BWN_PHY_WRITE(mac, rfctl[0], 0x140);
5893 BWN_PHY_WRITE(mac, rfctl[0], 0x110);
5896 BWN_PHY_WRITE(mac, rfctl[0], 0x180);
5898 BWN_PHY_WRITE(mac, rfctl[0], 0x120);
5902 BWN_PHY_WRITE(mac, rfctl[1], 0x148);
5904 BWN_PHY_WRITE(mac, rfctl[1], 0x114);
5907 BWN_RF_SETMASK(mac, B2055_C1_GENSPARE2, 0xFC,
5909 BWN_RF_SETMASK(mac, B2055_C2_GENSPARE2, 0xFC,
5947 bwn_nphy_rf_ctl_override(mac, 0x400, tmp[0], 3,
5949 bwn_nphy_force_rf_sequence(mac, BWN_RFSEQ_RESET2RX);
5950 bwn_nphy_stop_playback(mac);
5953 ret = bwn_nphy_tx_tone(mac, 4000,
5958 bwn_nphy_run_samples(mac, 160, 0xFFFF, 0, false,
5964 bwn_nphy_rx_iq_est(mac, &est, 1024, 32,
5975 bwn_nphy_calc_rx_iq_comp(mac, 1 << i);
5977 bwn_nphy_stop_playback(mac);
5984 BWN_RF_MASK(mac, B2055_C1_GENSPARE2, 0xFC);
5985 BWN_RF_MASK(mac, B2055_C2_GENSPARE2, 0xFC);
5986 BWN_PHY_WRITE(mac, rfctl[1], tmp[5]);
5987 BWN_PHY_WRITE(mac, rfctl[0], tmp[4]);
5988 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, tmp[3]);
5989 BWN_PHY_WRITE(mac, afectl_core, tmp[2]);
5990 BWN_PHY_WRITE(mac, BWN_NPHY_RFSEQCA, tmp[1]);
5996 bwn_nphy_rf_ctl_override(mac, 0x400, 0, 3, true);
5997 bwn_nphy_force_rf_sequence(mac, BWN_RFSEQ_RESET2RX);
5998 bwn_ntab_write_bulk(mac, BWN_NTAB16(7, 0x110), 2, gain_save);
6000 bwn_nphy_stay_in_carrier_search(mac, 0);
6005 static int bwn_nphy_rev3_cal_rx_iq(struct bwn_mac *mac,
6012 static int bwn_nphy_cal_rx_iq(struct bwn_mac *mac,
6015 if (mac->mac_phy.rev >= 7)
6018 if (mac->mac_phy.rev >= 3)
6019 return bwn_nphy_rev3_cal_rx_iq(mac, target, type, debug);
6021 return bwn_nphy_rev2_cal_rx_iq(mac, target, type, debug);
6025 static void bwn_nphy_set_rx_core_state(struct bwn_mac *mac, uint8_t mask)
6027 struct bwn_phy *phy = &mac->mac_phy;
6036 bwn_mac_suspend(mac);
6039 bwn_nphy_stay_in_carrier_search(mac, true);
6041 BWN_PHY_SETMASK(mac, BWN_NPHY_RFSEQCA, ~BWN_NPHY_RFSEQCA_RXEN,
6045 BWN_PHY_WRITE(mac, BWN_NPHY_HPANT_SWTHRES, 1);
6046 if (mac->mac_phy.rev >= 3) {
6050 BWN_PHY_WRITE(mac, BWN_NPHY_HPANT_SWTHRES, 0x1E);
6051 if (mac->mac_phy.rev >= 3) {
6056 bwn_nphy_force_rf_sequence(mac, BWN_RFSEQ_RESET2RX);
6059 bwn_nphy_stay_in_carrier_search(mac, false);
6061 bwn_mac_enable(mac);
6065 bwn_nphy_op_recalc_txpower(struct bwn_mac *mac, bool ignore_tssi)
6067 struct bwn_phy *phy = &mac->mac_phy;
6068 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
6069 struct ieee80211_channel *channel = bwn_get_channel(mac);
6070 struct bwn_softc *sc = mac->mac_sc;
6075 if (nphy->tx_pwr_last_recalc_freq == bwn_get_centre_freq(mac) &&
6080 bwn_ppr_clear(mac, ppr);
6083 bwn_ppr_load_max_from_sprom(mac, ppr, BWN_PHY_BAND_2G);
6087 max = INT_TO_Q52(bwn_get_chan_power(mac, channel));
6091 bwn_ppr_apply_max(mac, ppr, max);
6092 DPRINTF(mac->mac_sc, BWN_DEBUG_XMIT_POWER,
6094 Q52_ARG(bwn_ppr_get_max(mac, ppr)));
6100 if (bwn_current_band(mac) == BWN_BAND_2G)
6104 bwn_ppr_add(mac, ppr, -hw_gain);
6108 bwn_ppr_apply_min(mac, ppr, INT_TO_Q52(8));
6112 bwn_mac_suspend(mac);
6113 bwn_nphy_tx_power_ctl_setup(mac);
6115 BWN_WRITE_SETMASK4(mac, BWN_MACCTL, ~0, BWN_MACCTL_PHY_LOCK);
6116 BWN_READ_4(mac, BWN_MACCTL);
6119 bwn_nphy_tx_power_ctrl(mac, nphy->txpwrctrl);
6121 BWN_WRITE_SETMASK4(mac, BWN_MACCTL, ~BWN_MACCTL_PHY_LOCK, 0);
6122 bwn_mac_enable(mac);
6124 nphy->tx_pwr_last_recalc_freq = bwn_get_centre_freq(mac);
6135 static void bwn_nphy_update_mimo_config(struct bwn_mac *mac, int32_t preamble)
6137 uint16_t mimocfg = BWN_PHY_READ(mac, BWN_NPHY_MIMOCFG);
6145 BWN_PHY_WRITE(mac, BWN_NPHY_MIMOCFG, mimocfg);
6149 static void bwn_nphy_bphy_init(struct bwn_mac *mac)
6156 BWN_PHY_WRITE(mac, BWN_PHY_N_BMODE(0x88 + i), val);
6161 BWN_PHY_WRITE(mac, BWN_PHY_N_BMODE(0x98 + i), val);
6164 BWN_PHY_WRITE(mac, BWN_PHY_N_BMODE(0x38), 0x668);
6168 static int bwn_nphy_superswitch_init(struct bwn_mac *mac, bool init)
6172 if (mac->mac_phy.rev >= 7)
6175 if (mac->mac_phy.rev >= 3) {
6179 bwn_ntab_write(mac, BWN_NTAB16(9, 2), 0x211);
6180 bwn_ntab_write(mac, BWN_NTAB16(9, 3), 0x222);
6181 bwn_ntab_write(mac, BWN_NTAB16(9, 8), 0x144);
6182 bwn_ntab_write(mac, BWN_NTAB16(9, 12), 0x188);
6185 BWN_PHY_WRITE(mac, BWN_NPHY_GPIO_LOOEN, 0);
6186 BWN_PHY_WRITE(mac, BWN_NPHY_GPIO_HIOEN, 0);
6188 if ((error = bwn_gpio_control(mac, 0xfc00)))
6191 BWN_WRITE_SETMASK4(mac, BWN_MACCTL, ~BWN_MACCTL_GPOUT_MASK, 0);
6192 BWN_WRITE_SETMASK2(mac, BWN_GPIO_MASK, ~0, 0xFC00);
6193 BWN_WRITE_SETMASK2(mac, BWN_GPIO_CONTROL, (~0xFC00 & 0xFFFF),
6197 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
6198 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
6199 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
6200 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
6208 static int bwn_phy_initn(struct bwn_mac *mac)
6210 struct bwn_softc *sc = mac->mac_sc;
6211 struct bwn_phy *phy = &mac->mac_phy;
6223 if (mac->mac_phy.rev >= 3) {
6227 BWN_ERRPRINTF(mac->mac_sc, "Error reading %s from "
6235 if ((mac->mac_phy.rev >= 3) &&
6237 (bwn_current_band(mac) == BWN_BAND_2G))
6241 nphy->use_int_tx_iq_lo_cal = bwn_nphy_ipa(mac) ||
6246 bwn_nphy_tables_init(mac);
6251 if (mac->mac_phy.rev >= 3) {
6252 BWN_PHY_WRITE(mac, BWN_NPHY_TXF_40CO_B1S1, 0);
6253 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_OVER, 0);
6255 BWN_PHY_WRITE(mac, BWN_NPHY_REV7_RF_CTL_OVER3, 0);
6256 BWN_PHY_WRITE(mac, BWN_NPHY_REV7_RF_CTL_OVER4, 0);
6257 BWN_PHY_WRITE(mac, BWN_NPHY_REV7_RF_CTL_OVER5, 0);
6258 BWN_PHY_WRITE(mac, BWN_NPHY_REV7_RF_CTL_OVER6, 0);
6264 BWN_PHY_WRITE(mac, BWN_NPHY_TXF_40CO_B1S0, 0);
6265 BWN_PHY_WRITE(mac, BWN_NPHY_TXF_40CO_B32S1, 0);
6267 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_OVER, 0);
6269 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC1, 0);
6270 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC2, 0);
6271 if (mac->mac_phy.rev < 6) {
6272 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC3, 0);
6273 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC4, 0);
6275 BWN_PHY_MASK(mac, BWN_NPHY_RFSEQMODE,
6278 if (mac->mac_phy.rev >= 3)
6279 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER1, 0);
6280 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, 0);
6282 if (mac->mac_phy.rev <= 2) {
6283 tmp = (mac->mac_phy.rev == 2) ? 0x3B : 0x40;
6284 BWN_PHY_SETMASK(mac, BWN_NPHY_BPHY_CTL3,
6288 BWN_PHY_WRITE(mac, BWN_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
6289 BWN_PHY_WRITE(mac, BWN_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
6294 BWN_PHY_WRITE(mac, BWN_NPHY_TXREALFD, 0xA0);
6296 BWN_PHY_WRITE(mac, BWN_NPHY_TXREALFD, 0xB8);
6297 BWN_PHY_WRITE(mac, BWN_NPHY_MIMO_CRSTXEXT, 0xC8);
6298 BWN_PHY_WRITE(mac, BWN_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
6299 BWN_PHY_WRITE(mac, BWN_NPHY_TXRIFS_FRDEL, 0x30);
6302 bwn_nphy_update_mimo_config(mac, nphy->preamble_override);
6304 bwn_nphy_update_txrx_chain(mac);
6307 BWN_PHY_WRITE(mac, BWN_NPHY_DUP40_GFBL, 0xAA8);
6308 BWN_PHY_WRITE(mac, BWN_NPHY_DUP40_BL, 0x9A4);
6311 tmp2 = bwn_current_band(mac);
6312 if (bwn_nphy_ipa(mac)) {
6313 BWN_PHY_SET(mac, BWN_NPHY_PAPD_EN0, 0x1);
6314 BWN_PHY_SETMASK(mac, BWN_NPHY_EPS_TABLE_ADJ0, 0x007F,
6316 BWN_PHY_SET(mac, BWN_NPHY_PAPD_EN1, 0x1);
6317 BWN_PHY_SETMASK(mac, BWN_NPHY_EPS_TABLE_ADJ1, 0x007F,
6319 bwn_nphy_int_pa_set_tx_dig_filters(mac);
6321 bwn_nphy_ext_pa_set_tx_dig_filters(mac);
6324 if ((error = bwn_nphy_workarounds(mac)))
6328 bwn_phy_force_clock(mac, 1);
6329 tmp = BWN_PHY_READ(mac, BWN_NPHY_BBCFG);
6330 BWN_PHY_WRITE(mac, BWN_NPHY_BBCFG, tmp | BWN_NPHY_BBCFG_RSTCCA);
6331 BWN_PHY_WRITE(mac, BWN_NPHY_BBCFG, tmp & ~BWN_NPHY_BBCFG_RSTCCA);
6332 bwn_phy_force_clock(mac, 0);
6334 bwn_mac_phy_clock_set(mac, true);
6337 bwn_nphy_pa_override(mac, false);
6338 bwn_nphy_force_rf_sequence(mac, BWN_RFSEQ_RX2TX);
6339 bwn_nphy_force_rf_sequence(mac, BWN_RFSEQ_RESET2RX);
6340 bwn_nphy_pa_override(mac, true);
6343 bwn_nphy_classifier(mac, 0, 0);
6344 bwn_nphy_read_clip_detection(mac, clip);
6345 if (bwn_current_band(mac) == BWN_BAND_2G)
6346 bwn_nphy_bphy_init(mac);
6349 bwn_nphy_tx_power_ctrl(mac, false);
6350 if ((error = bwn_nphy_tx_power_fix(mac)))
6352 bwn_nphy_tx_power_ctl_idle_tssi(mac);
6353 bwn_nphy_tx_power_ctl_setup(mac);
6354 bwn_nphy_tx_gain_table_upload(mac);
6357 bwn_nphy_set_rx_core_state(mac, nphy->phyrxchain);
6363 if (bwn_current_band(mac) == BWN_BAND_2G)
6369 bwn_nphy_rssi_cal(mac);
6371 bwn_nphy_restore_rssi_cal(mac);
6373 bwn_nphy_rssi_cal(mac);
6377 if (bwn_current_band(mac) == BWN_BAND_2G)
6386 target = bwn_nphy_get_tx_gains(mac);
6389 error = bwn_nphy_superswitch_init(mac, true);
6394 bwn_nphy_rssi_cal(mac);
6401 target = bwn_nphy_get_tx_gains(mac);
6403 if (!bwn_nphy_cal_tx_iq_lo(mac, target, true, false))
6404 if (bwn_nphy_cal_rx_iq(mac, target, 2, 0) == 0)
6405 bwn_nphy_save_cal(mac);
6409 bwn_nphy_restore_cal(mac);
6413 bwn_nphy_tx_pwr_ctrl_coef_setup(mac);
6414 bwn_nphy_tx_power_ctrl(mac, tx_pwr_state);
6415 BWN_PHY_WRITE(mac, BWN_NPHY_TXMACIF_HOLDOFF, 0x0015);
6416 BWN_PHY_WRITE(mac, BWN_NPHY_TXMACDELAY, 0x0320);
6418 BWN_PHY_WRITE(mac, BWN_NPHY_PLOAD_CSENSE_EXTLEN, 0x0032);
6419 bwn_nphy_tx_lpf_bw(mac);
6421 bwn_nphy_spur_workaround(mac);
6430 static void bwn_chantab_phy_upload(struct bwn_mac *mac,
6433 BWN_PHY_WRITE(mac, BWN_NPHY_BW1A, e->phy_bw1a);
6434 BWN_PHY_WRITE(mac, BWN_NPHY_BW2, e->phy_bw2);
6435 BWN_PHY_WRITE(mac, BWN_NPHY_BW3, e->phy_bw3);
6436 BWN_PHY_WRITE(mac, BWN_NPHY_BW4, e->phy_bw4);
6437 BWN_PHY_WRITE(mac, BWN_NPHY_BW5, e->phy_bw5);
6438 BWN_PHY_WRITE(mac, BWN_NPHY_BW6, e->phy_bw6);
6442 static void bwn_nphy_pmu_spur_avoid(struct bwn_mac *mac,
6445 struct bwn_softc *sc = mac->mac_sc;
6451 BWN_ERRPRINTF(mac->mac_sc, "no PMU; cannot configure spurious "
6463 static int bwn_nphy_channel_setup(struct bwn_mac *mac,
6467 struct bwn_softc *sc = mac->mac_sc;
6468 struct bwn_phy *phy = &mac->mac_phy;
6469 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
6474 if (bwn_channel_band(mac, new_channel) == BWN_BAND_5G) {
6477 BWN_PHY_MASK(mac, BWN_NPHY_BANDCTL, ~BWN_NPHY_BANDCTL_5GHZ);
6479 tmp16 = BWN_READ_2(mac, BWN_PSM_PHY_HDR);
6480 BWN_WRITE_2(mac, BWN_PSM_PHY_HDR, tmp16 | 4);
6482 BWN_PHY_SET(mac, BWN_PHY_B_BBCFG,
6484 BWN_WRITE_2(mac, BWN_PSM_PHY_HDR, tmp16);
6485 BWN_PHY_SET(mac, BWN_NPHY_BANDCTL, BWN_NPHY_BANDCTL_5GHZ);
6486 } else if (bwn_channel_band(mac, new_channel) == BWN_BAND_2G) {
6488 BWN_PHY_MASK(mac, BWN_NPHY_BANDCTL, ~BWN_NPHY_BANDCTL_5GHZ);
6489 tmp16 = BWN_READ_2(mac, BWN_PSM_PHY_HDR);
6490 BWN_WRITE_2(mac, BWN_PSM_PHY_HDR, tmp16 | 4);
6492 BWN_PHY_MASK(mac, BWN_PHY_B_BBCFG,
6494 BWN_WRITE_2(mac, BWN_PSM_PHY_HDR, tmp16);
6496 BWN_ERRPRINTF(mac->mac_sc, "%s: unknown band?\n", __func__);
6499 bwn_chantab_phy_upload(mac, e);
6502 bwn_nphy_classifier(mac, 2, 0);
6503 BWN_PHY_SET(mac, BWN_PHY_B_TEST, 0x0800);
6505 bwn_nphy_classifier(mac, 2, 2);
6506 if (bwn_channel_band(mac, new_channel) == BWN_BAND_2G)
6507 BWN_PHY_MASK(mac, BWN_PHY_B_TEST, ~0x840);
6511 if ((error = bwn_nphy_tx_power_fix(mac)))
6515 if (mac->mac_phy.rev < 3)
6516 bwn_nphy_adjust_lna_gain_table(mac);
6518 bwn_nphy_tx_lpf_bw(mac);
6520 if (mac->mac_phy.rev >= 3 &&
6521 mac->mac_phy.phy_n->spur_avoid != BWN_SPUR_AVOID_DISABLE) {
6524 if (mac->mac_phy.phy_n->spur_avoid == BWN_SPUR_AVOID_FORCE) {
6535 if (!bwn_is_40mhz(mac)) { /* 20MHz */
6543 if (!bwn_is_40mhz(mac)) { /* 20MHz */
6554 bwn_nphy_pmu_spur_avoid(mac, spuravoid);
6556 bwn_mac_switch_freq(mac, spuravoid);
6558 if (mac->mac_phy.rev == 3 || mac->mac_phy.rev == 4)
6559 bwn_wireless_core_phy_pll_reset(mac);
6562 BWN_PHY_SET(mac, BWN_NPHY_BBCFG, BWN_NPHY_BBCFG_RSTRX);
6564 BWN_PHY_MASK(mac, BWN_NPHY_BBCFG,
6567 bwn_nphy_reset_cca(mac);
6572 BWN_PHY_WRITE(mac, BWN_NPHY_NDATAT_DUP40, 0x3830);
6575 bwn_nphy_spur_workaround(mac);
6581 static int bwn_nphy_set_channel(struct bwn_mac *mac,
6585 struct bwn_phy *phy = &mac->mac_phy;
6599 r2057_get_chantabent_rev7(mac, bwn_get_chan_centre_freq(mac, channel),
6604 tabent_r3 = bwn_nphy_get_chantabent_rev3(mac,
6605 bwn_get_chan_centre_freq(mac, channel));
6609 tabent_r2 = bwn_nphy_get_chantabent_rev2(mac,
6628 BWN_PHY_SET(mac, BWN_NPHY_RXCTL, BWN_NPHY_RXCTL_BSELU20);
6630 BWN_PHY_SET(mac, 0x310, 0x8000);
6632 BWN_PHY_MASK(mac, BWN_NPHY_RXCTL, ~BWN_NPHY_RXCTL_BSELU20);
6634 BWN_PHY_MASK(mac, 0x310, (uint16_t)~0x8000);
6645 tmp = (bwn_channel_band(mac, channel) == BWN_BAND_5G) ? 2 : 0;
6646 BWN_RF_SETMASK(mac, R2057_TIA_CONFIG_CORE0, ~2, tmp);
6647 BWN_RF_SETMASK(mac, R2057_TIA_CONFIG_CORE1, ~2, tmp);
6650 bwn_radio_2057_setup(mac, tabent_r7, tabent_r7_2g);
6651 error = bwn_nphy_channel_setup(mac, phy_regs, channel);
6653 tmp = (bwn_channel_band(mac, channel) == BWN_BAND_5G) ? 4 : 0;
6654 BWN_RF_SETMASK(mac, 0x08, 0xFFFB, tmp);
6655 bwn_radio_2056_setup(mac, tabent_r3);
6656 error = bwn_nphy_channel_setup(mac, &(tabent_r3->phy_regs),
6659 tmp = (bwn_channel_band(mac, channel) == BWN_BAND_5G) ? 0x0020 : 0x0050;
6660 BWN_RF_SETMASK(mac, B2055_MASTER1, 0xFF8F, tmp);
6661 bwn_radio_2055_setup(mac, tabent_r2);
6662 error = bwn_nphy_channel_setup(mac, &(tabent_r2->phy_regs),
6674 bwn_nphy_op_allocate(struct bwn_mac *mac)
6682 mac->mac_phy.phy_n = nphy;
6688 bwn_nphy_op_prepare_structs(struct bwn_mac *mac)
6690 struct bwn_softc *sc = mac->mac_sc;
6691 struct bwn_phy *phy = &mac->mac_phy;
6712 if (mac->mac_phy.rev >= 3 ||
6718 if (mac->mac_phy.rev >= 2 &&
6729 if (mac->mac_phy.rev >= 3) {
6735 BWN_ERRPRINTF(mac->mac_sc, "Error reading 2GHz EPA "
6743 BWN_ERRPRINTF(mac->mac_sc, "Error reading 5GHz EPA "
6756 bwn_nphy_op_free(struct bwn_mac *mac)
6758 struct bwn_phy *phy = &mac->mac_phy;
6766 bwn_nphy_op_init(struct bwn_mac *mac)
6768 return bwn_phy_initn(mac);
6771 static inline void check_phyreg(struct bwn_mac *mac, uint16_t offset)
6776 BWN_ERRPRINTF(mac->mac_sc, "Invalid OFDM PHY access at "
6781 BWN_ERRPRINTF(mac->mac_sc, "Invalid EXT-G PHY access at "
6788 bwn_nphy_op_maskset(struct bwn_mac *mac, uint16_t reg, uint16_t mask,
6791 check_phyreg(mac, reg);
6792 BWN_WRITE_2_F(mac, BWN_PHYCTL, reg);
6793 BWN_WRITE_SETMASK2(mac, BWN_PHYDATA, mask, set);
6798 bwn_nphy_op_radio_read(struct bwn_mac *mac, uint16_t reg)
6801 if (mac->mac_phy.rev < 7 && reg == 1) {
6802 BWN_ERRPRINTF(mac->mac_sc, "%s: bad reg access\n", __func__);
6805 if (mac->mac_phy.rev >= 7)
6810 BWN_WRITE_2_F(mac, BWN_RFCTL, reg);
6811 return BWN_READ_2(mac, BWN_RFDATALO);
6817 bwn_nphy_op_radio_write(struct bwn_mac *mac, uint16_t reg, uint16_t value)
6820 if (mac->mac_phy.rev < 7 && reg == 1) {
6821 BWN_ERRPRINTF(mac->mac_sc, "%s: bad reg access\n", __func__);
6824 BWN_WRITE_2_F(mac, BWN_RFCTL, reg);
6825 BWN_WRITE_2(mac, BWN_RFDATALO, value);
6831 bwn_nphy_op_software_rfkill(struct bwn_mac *mac, bool active)
6833 struct bwn_phy *phy = &mac->mac_phy;
6835 if (BWN_READ_4(mac, BWN_MACCTL) & BWN_MACCTL_ON)
6836 BWN_ERRPRINTF(mac->mac_sc, "MAC not suspended\n");
6838 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET | BWN_DEBUG_PHY,
6840 phy->rev, mac->mac_phy.rf_on, active);
6852 // if (!mac->mac_phy.rf_on)
6853 bwn_radio_2057_init(mac);
6854 bwn_switch_channel(mac, bwn_get_chan(mac));
6856 // if (!mac->mac_phy.rf_on)
6857 bwn_radio_init2056(mac);
6858 bwn_switch_channel(mac, bwn_get_chan(mac));
6860 bwn_radio_init2055(mac);
6866 BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_CMD,
6871 BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_CMD,
6874 BWN_RF_MASK(mac, 0x09, ~0x2);
6876 BWN_RF_WRITE(mac, 0x204D, 0);
6877 BWN_RF_WRITE(mac, 0x2053, 0);
6878 BWN_RF_WRITE(mac, 0x2058, 0);
6879 BWN_RF_WRITE(mac, 0x205E, 0);
6880 BWN_RF_MASK(mac, 0x2062, ~0xF0);
6881 BWN_RF_WRITE(mac, 0x2064, 0);
6883 BWN_RF_WRITE(mac, 0x304D, 0);
6884 BWN_RF_WRITE(mac, 0x3053, 0);
6885 BWN_RF_WRITE(mac, 0x3058, 0);
6886 BWN_RF_WRITE(mac, 0x305E, 0);
6887 BWN_RF_MASK(mac, 0x3062, ~0xF0);
6888 BWN_RF_WRITE(mac, 0x3064, 0);
6895 bwn_nphy_op_switch_analog(struct bwn_mac *mac, bool on)
6897 struct bwn_phy *phy = &mac->mac_phy;
6903 device_printf(mac->mac_sc->sc_dev, "%s: TODO\n", __func__);
6906 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C1, core);
6907 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER1, override);
6908 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C2, core);
6909 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, override);
6911 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER1, override);
6912 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C1, core);
6913 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, override);
6914 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C2, core);
6917 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, override);
6922 bwn_nphy_op_switch_channel(struct bwn_mac *mac, unsigned int new_channel)
6924 struct ieee80211_channel *channel = bwn_get_channel(mac);
6925 bwn_chan_type_t channel_type = bwn_get_chan_type(mac, NULL);
6927 if (bwn_current_band(mac) == BWN_BAND_2G) {
6935 return bwn_nphy_set_channel(mac, channel, channel_type);
6940 bwn_nphy_op_get_default_chan(struct bwn_mac *mac)
6942 if (bwn_current_band(mac) == BWN_BAND_2G)