Lines Matching refs:mcr
1237 uint16_t mcr;
1242 mcr = CSR_READ_2(sc, VTE_MCR0);
1243 mcr &= ~(MCR0_FC_ENB | MCR0_FULL_DUPLEX);
1245 mcr |= MCR0_FULL_DUPLEX;
1248 mcr |= MCR0_FC_ENB;
1256 mcr |= MCR0_FC_ENB;
1259 CSR_WRITE_2(sc, VTE_MCR0, mcr);
1608 uint16_t mcr;
1611 mcr = CSR_READ_2(sc, VTE_MCR1);
1612 CSR_WRITE_2(sc, VTE_MCR1, mcr | MCR1_MAC_RESET);
1619 device_printf(sc->vte_dev, "reset timeout(0x%04x)!\n", mcr);
1828 uint16_t mcr;
1834 mcr = CSR_READ_2(sc, VTE_MCR0);
1835 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) !=
1837 mcr |= MCR0_RX_ENB | MCR0_TX_ENB;
1838 CSR_WRITE_2(sc, VTE_MCR0, mcr);
1840 mcr = CSR_READ_2(sc, VTE_MCR0);
1841 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) ==
1848 "could not enable RX/TX MAC(0x%04x)!\n", mcr);
1855 uint16_t mcr;
1861 mcr = CSR_READ_2(sc, VTE_MCR0);
1862 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) != 0) {
1863 mcr &= ~(MCR0_RX_ENB | MCR0_TX_ENB);
1864 CSR_WRITE_2(sc, VTE_MCR0, mcr);
1866 mcr = CSR_READ_2(sc, VTE_MCR0);
1867 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) == 0)
1873 "could not disable RX/TX MAC(0x%04x)!\n", mcr);
1997 uint16_t mcr;
2012 mcr = CSR_READ_2(sc, VTE_MCR0);
2013 mcr &= ~(MCR0_PROMISC | MCR0_MULTICAST);
2014 mcr |= MCR0_BROADCAST_DIS;
2016 mcr &= ~MCR0_BROADCAST_DIS;
2019 mcr |= MCR0_PROMISC;
2021 mcr |= MCR0_MULTICAST;
2032 mcr |= MCR0_MULTICAST;
2049 CSR_WRITE_2(sc, VTE_MCR0, mcr);