Lines Matching refs:CSR_SETBIT_1
251 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD);
252 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/);
258 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD);
376 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD);
412 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD);
443 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK);
456 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR);
471 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA);
481 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE);
498 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK);
501 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8),
510 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR);
2067 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES);
2071 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128);
2073 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK);
2078 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET);
2081 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS);
2242 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE);
2247 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE);
2249 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE);
2888 CSR_SETBIT_1(sc, VGE_DIAGCTL,