Lines Matching defs:encp
90 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
99 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
102 encp->enc_external_port = (uint8_t)enp->en_mcdi.em_emip.emi_port;
109 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
111 encp->enc_board_type = board_type;
118 encp->enc_hw_pf_count = 1;
121 encp->enc_clk_mult = 1;
127 encp->enc_clk_mult = 2;
131 encp->enc_evq_timer_quantum_ns =
132 EFX_EVQ_SIENA_TIMER_QUANTUM_NS / encp->enc_clk_mult;
133 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
137 encp->enc_rx_prefix_size = 16;
140 encp->enc_rx_buf_align_start = 1;
141 encp->enc_rx_buf_align_end = 1;
144 encp->enc_rx_push_align = 1;
148 encp->enc_rx_scale_max_exclusive_contexts = 1;
150 encp->enc_rx_scale_hash_alg_mask |= (1U << EFX_RX_HASHALG_LFSR);
151 encp->enc_rx_scale_hash_alg_mask |= (1U << EFX_RX_HASHALG_TOEPLITZ);
157 encp->enc_rx_scale_l4_hash_supported = B_TRUE;
160 encp->enc_rx_scale_additional_modes_supported = B_FALSE;
163 encp->enc_tx_dma_desc_size_max = EFX_MASK32(FSF_AZ_TX_KER_BYTE_COUNT);
165 encp->enc_tx_dma_desc_boundary = 4096;
177 encp->enc_evq_limit = nevq;
178 encp->enc_rxq_limit = MIN(EFX_RXQ_LIMIT_TARGET, nrxq);
179 encp->enc_txq_limit = MIN(EFX_TXQ_LIMIT_TARGET, ntxq);
181 encp->enc_txq_max_ndescs = 4096;
183 encp->enc_buftbl_limit = SIENA_SRAM_ROWS -
184 (encp->enc_txq_limit * EFX_TXQ_DC_NDESCS(EFX_TXQ_DC_SIZE)) -
185 (encp->enc_rxq_limit * EFX_RXQ_DC_NDESCS(EFX_RXQ_DC_SIZE));
187 encp->enc_hw_tx_insert_vlan_enabled = B_FALSE;
188 encp->enc_fw_assisted_tso_enabled = B_FALSE;
189 encp->enc_fw_assisted_tso_v2_enabled = B_FALSE;
190 encp->enc_fw_assisted_tso_v2_n_contexts = 0;
191 encp->enc_allow_set_mac_with_installed_filters = B_TRUE;
192 encp->enc_rx_packed_stream_supported = B_FALSE;
193 encp->enc_rx_var_packed_stream_supported = B_FALSE;
194 encp->enc_rx_es_super_buffer_supported = B_FALSE;
195 encp->enc_fw_subvariant_no_tx_csum_supported = B_FALSE;
198 encp->enc_required_pcie_bandwidth_mbps = 2 * 10000;
199 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN2;
201 encp->enc_nvram_update_verify_result_supported = B_FALSE;
203 encp->enc_mac_stats_nstats = MC_CMD_MAC_NSTATS;
205 encp->enc_filter_action_flag_supported = B_FALSE;
206 encp->enc_filter_action_mark_supported = B_FALSE;
207 encp->enc_filter_action_mark_max = 0;
224 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
234 siena_phy_decode_stats(enp, encp->enc_mcdi_phy_stat_mask,
235 NULL, &encp->enc_phy_stat_mask, NULL);
322 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
390 encp->enc_features = enp->en_features;