Lines Matching defs:encp
100 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
130 encp->enc_bug35388_workaround = B_TRUE;
132 encp->enc_bug35388_workaround = B_FALSE;
143 encp->enc_bug41750_workaround = B_TRUE;
147 encp->enc_bug41750_workaround = B_TRUE;
149 encp->enc_bug41750_workaround = B_FALSE;
151 encp->enc_bug41750_workaround = B_FALSE;
155 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
157 encp->enc_bug41750_workaround = B_TRUE;
172 encp->enc_bug26807_workaround = B_TRUE;
187 encp->enc_bug26807_workaround = B_FALSE;
189 encp->enc_bug26807_workaround = B_FALSE;
202 encp->enc_evq_timer_quantum_ns = 1536000UL / sysclk; /* 1536 cycles */
203 if (encp->enc_bug35388_workaround) {
204 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
207 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
211 encp->enc_bug61265_workaround = B_FALSE; /* Medford only */
214 encp->enc_bug61297_workaround = B_TRUE;
217 encp->enc_rx_buf_align_start = 1;
218 encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */
224 encp->enc_txq_max_ndescs = encp->enc_bug35388_workaround ? 2048 : 4096;
227 encp->enc_piobuf_limit = HUNT_PIOBUF_NBUFS;
228 encp->enc_piobuf_size = HUNT_PIOBUF_SIZE;
229 encp->enc_piobuf_min_alloc_size = HUNT_MIN_PIO_ALLOC_SIZE;
233 encp->enc_required_pcie_bandwidth_mbps = bandwidth;
236 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;