Lines Matching refs:vals
137 uint16_t rx[2][2], struct r92c_iq_cal_reg_vals *vals)
151 vals->adda[i] = rtwn_bb_read(sc, reg_adda[i]);
153 vals->txpause = rtwn_read_1(sc, R92C_TXPAUSE);
154 vals->bcn_ctrl[0] = rtwn_read_1(sc, R92C_BCN_CTRL(0));
155 vals->bcn_ctrl[1] = rtwn_read_1(sc, R92C_BCN_CTRL(1));
156 vals->gpio_muxcfg = rtwn_read_4(sc, R92C_GPIO_MUXCFG);
177 vals->cck0_afesetting = rtwn_bb_read(sc, R92C_CCK0_AFESETTING);
178 vals->ofdm0_trxpathena =
180 vals->ofdm0_trmuxpar = rtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR);
181 vals->fpga0_rfifacesw0 =
183 vals->fpga0_rfifacesw1 =
185 vals->fpga0_rfifaceoe0 =
187 vals->fpga0_rfifaceoe1 =
189 vals->config_ant0 = rtwn_bb_read(sc, R92C_CONFIG_ANT(0));
190 vals->config_ant1 = rtwn_bb_read(sc, R92C_CONFIG_ANT(1));
209 vals->bcn_ctrl[0] & ~R92C_BCN_CTRL_EN_BCN);
211 vals->bcn_ctrl[1] & ~R92C_BCN_CTRL_EN_BCN);
213 vals->gpio_muxcfg & ~R92C_GPIO_MUXCFG_ENBT);
268 rtwn_bb_write(sc, R92C_CCK0_AFESETTING, vals->cck0_afesetting);
269 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, vals->ofdm0_trxpathena);
270 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(0), vals->fpga0_rfifacesw0);
271 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), vals->fpga0_rfifacesw1);
272 rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, vals->ofdm0_trmuxpar);
273 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(0), vals->fpga0_rfifaceoe0);
274 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(1), vals->fpga0_rfifaceoe1);
275 rtwn_bb_write(sc, R92C_CONFIG_ANT(0), vals->config_ant0);
276 rtwn_bb_write(sc, R92C_CONFIG_ANT(1), vals->config_ant1);
290 rtwn_bb_write(sc, reg_adda[i], vals->adda[i]);
292 rtwn_write_1(sc, R92C_TXPAUSE, vals->txpause);
293 rtwn_write_1(sc, R92C_BCN_CTRL(0), vals->bcn_ctrl[0]);
294 rtwn_write_1(sc, R92C_BCN_CTRL(1), vals->bcn_ctrl[1]);
295 rtwn_write_4(sc, R92C_GPIO_MUXCFG, vals->gpio_muxcfg);
383 struct r92c_iq_cal_reg_vals vals;
389 r92c_iq_calib_run(sc, n, tx[n], rx[n], &vals);