Lines Matching refs:vals
159 uint16_t rx[2], struct r88e_iq_cal_reg_vals *vals)
173 vals->adda[i] = rtwn_bb_read(sc, reg_adda[i]);
175 vals->txpause = rtwn_read_1(sc, R92C_TXPAUSE);
176 vals->bcn_ctrl[0] = rtwn_read_1(sc, R92C_BCN_CTRL(0));
177 vals->bcn_ctrl[1] = rtwn_read_1(sc, R92C_BCN_CTRL(1));
178 vals->gpio_muxcfg = rtwn_read_4(sc, R92C_GPIO_MUXCFG);
194 vals->cck0_afesetting = rtwn_bb_read(sc, R92C_CCK0_AFESETTING);
195 vals->ofdm0_trxpathena =
197 vals->ofdm0_trmuxpar = rtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR);
198 vals->fpga0_rfifacesw0 =
200 vals->fpga0_rfifacesw1 =
202 vals->fpga0_rfifaceoe0 =
204 vals->fpga0_rfifaceoe1 =
206 vals->config_ant0 = rtwn_bb_read(sc, R92C_CONFIG_ANT(0));
207 vals->config_ant1 = rtwn_bb_read(sc, R92C_CONFIG_ANT(1));
221 vals->bcn_ctrl[0] & ~R92C_BCN_CTRL_EN_BCN);
223 vals->bcn_ctrl[1] & ~R92C_BCN_CTRL_EN_BCN);
225 vals->gpio_muxcfg & ~R92C_GPIO_MUXCFG_ENBT);
260 rtwn_bb_write(sc, R92C_CCK0_AFESETTING, vals->cck0_afesetting);
261 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, vals->ofdm0_trxpathena);
262 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(0), vals->fpga0_rfifacesw0);
263 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), vals->fpga0_rfifacesw1);
264 rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, vals->ofdm0_trmuxpar);
265 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(0), vals->fpga0_rfifaceoe0);
266 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(1), vals->fpga0_rfifaceoe1);
267 rtwn_bb_write(sc, R92C_CONFIG_ANT(0), vals->config_ant0);
268 rtwn_bb_write(sc, R92C_CONFIG_ANT(1), vals->config_ant1);
280 rtwn_bb_write(sc, reg_adda[i], vals->adda[i]);
282 rtwn_write_1(sc, R92C_TXPAUSE, vals->txpause);
283 rtwn_write_1(sc, R92C_BCN_CTRL(0), vals->bcn_ctrl[0]);
284 rtwn_write_1(sc, R92C_BCN_CTRL(1), vals->bcn_ctrl[1]);
285 rtwn_write_4(sc, R92C_GPIO_MUXCFG, vals->gpio_muxcfg);
356 struct r88e_iq_cal_reg_vals vals;
365 r88e_iq_calib_run(sc, n, tx[n], rx[n], &vals);