Lines Matching defs:cfg_bits
74 static int qla_set_port_config(qla_host_t *ha, uint32_t cfg_bits);
75 static int qla_get_port_config(qla_host_t *ha, uint32_t *cfg_bits);
139 uint32_t cfg_bits;
149 err = qla_get_port_config(ha, &cfg_bits);
155 cfg_bits |= Q8_PORT_CFG_BITS_DCBX_ENABLE;
157 cfg_bits &= ~Q8_PORT_CFG_BITS_DCBX_ENABLE;
161 cfg_bits &= ~Q8_PORT_CFG_BITS_PAUSE_CFG_MASK;
164 cfg_bits |= Q8_PORT_CFG_BITS_PAUSE_DISABLED;
166 cfg_bits |= Q8_PORT_CFG_BITS_PAUSE_STD;
168 cfg_bits |= Q8_PORT_CFG_BITS_PAUSE_PPM;
172 cfg_bits &= ~Q8_PORT_CFG_BITS_STDPAUSE_DIR_MASK;
175 cfg_bits |= Q8_PORT_CFG_BITS_STDPAUSE_XMT_RCV;
177 cfg_bits |= Q8_PORT_CFG_BITS_STDPAUSE_XMT;
179 cfg_bits |= Q8_PORT_CFG_BITS_STDPAUSE_RCV;
183 err = qla_set_port_config(ha, cfg_bits);
190 err = qla_get_port_config(ha, &cfg_bits);
4076 qla_set_port_config(qla_host_t *ha, uint32_t cfg_bits)
4093 pcfg->cfg_bits = cfg_bits;
4095 device_printf(dev, "%s: cfg_bits"
4098 ((cfg_bits & Q8_PORT_CFG_BITS_STDPAUSE_DIR_MASK)>>20),
4099 ((cfg_bits & Q8_PORT_CFG_BITS_PAUSE_CFG_MASK) >> 5),
4100 ((cfg_bits & Q8_PORT_CFG_BITS_DCBX_ENABLE) ? 1: 0));
4183 qla_get_port_config(qla_host_t *ha, uint32_t *cfg_bits)
4215 device_printf(dev, "%s: [cfg_bits, port type]"
4218 pcfg_rsp->cfg_bits, pcfg_rsp->phys_port_type,
4219 ((pcfg_rsp->cfg_bits & Q8_PORT_CFG_BITS_STDPAUSE_DIR_MASK)>>20),
4220 ((pcfg_rsp->cfg_bits & Q8_PORT_CFG_BITS_PAUSE_CFG_MASK) >> 5),
4221 ((pcfg_rsp->cfg_bits & Q8_PORT_CFG_BITS_DCBX_ENABLE) ? 1: 0)
4224 *cfg_bits = pcfg_rsp->cfg_bits;