Lines Matching refs:PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X124_K2_E5

26895 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X124_K2_E5                                                           0x0011f0UL //Access:RW   DataWidth:0x8    // Bits 12:8: txdrv_c1_in[4:0] Bits 15:13: txdrv_c2_in[2:0]