Lines Matching refs:PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X30_MSM_CMU_REF_CLK_EN_OUT_OVR_O_K2_E5

28972   #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X30_MSM_CMU_REF_CLK_EN_OUT_OVR_O_K2_E5                             (0x3<<2) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - REF clock output enable