Lines Matching refs:PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X73_K2_E5
33662 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X73_K2_E5 0x002124UL //Access:RW DataWidth:0x8 // Multi Field Register.