Lines Matching refs:PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X23_K2_E5
33574 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X23_K2_E5 0x00205cUL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern