Lines Matching refs:PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X127_K2_E5
32822 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X127_K2_E5 0x0019fcUL //Access:RW DataWidth:0x8 // Multi Field Register.