Lines Matching refs:PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X268_K2_E5
32100 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X268_K2_E5 0x001430UL //Access:RW DataWidth:0x8 // Multi Field Register.