Lines Matching refs:PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X248_AHB_CDFE_DLL_FINE_MASK_9_8_K2_E5
30945 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X248_AHB_CDFE_DLL_FINE_MASK_9_8_K2_E5 (0x3<<0) //