Lines Matching refs:PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X155_K2_E5
30785 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X155_K2_E5 0x000a6cUL //Access:RW DataWidth:0x8 // Multi Field Register.