Lines Matching refs:PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_S2P_O_K2_E5_SHIFT
35873 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_S2P_O_K2_E5_SHIFT 4