Lines Matching refs:PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_LNREG_O_K2_E5_SHIFT
35777 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_LNREG_O_K2_E5_SHIFT 3